[LLVMbugs] [Bug 18466] New: [ARM] Invalid Post-RA scheduling due to missing of implicit reg use

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=18466

            Bug ID: 18466
           Summary: [ARM] Invalid Post-RA scheduling due to missing of
                    implicit reg use
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: weimingz at codeaurora.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

We encounter a runtime error. After debugging the generated code, we find that
it's due to mis pos-ra scheduling. The root cause is, when expanding neon
pseudo instrs, it misses the implicit uses of sub regs, which may further cause
post RA scheduler reorder instructions that
breakes anti dependency.

For example:
  VST1d64QPseudo %R0<kill>, 16, %Q9_Q10, pred:14, pred:%noreg
will be expanded to
  VST1d64Q %R0<kill>, 16, %D18, pred:14, pred:%noreg;

An instruction that defines %D20 may be scheduled before the store by
mistake.

What we expect is VST1d64Q %R0<kill>, 8, %D18, pred:14, pred:%noreg,
%Q9_Q10<imp-use>

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