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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [ARM] Invalid Post-RA scheduling due to missing of implicit reg use"
href="http://llvm.org/bugs/show_bug.cgi?id=18466">18466</a>
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<th>Summary</th>
<td>[ARM] Invalid Post-RA scheduling due to missing of implicit reg use
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<th>Product</th>
<td>new-bugs
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>new bugs
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>weimingz@codeaurora.org
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
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<th>Classification</th>
<td>Unclassified
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<p>
<div>
<pre>We encounter a runtime error. After debugging the generated code, we find that
it's due to mis pos-ra scheduling. The root cause is, when expanding neon
pseudo instrs, it misses the implicit uses of sub regs, which may further cause
post RA scheduler reorder instructions that
breakes anti dependency.
For example:
VST1d64QPseudo %R0<kill>, 16, %Q9_Q10, pred:14, pred:%noreg
will be expanded to
VST1d64Q %R0<kill>, 16, %D18, pred:14, pred:%noreg;
An instruction that defines %D20 may be scheduled before the store by
mistake.
What we expect is VST1d64Q %R0<kill>, 8, %D18, pred:14, pred:%noreg,
%Q9_Q10<imp-use></pre>
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