[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)
Craig Topper via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Mar 24 20:28:18 PDT 2024
================
@@ -483,90 +482,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
// VR->VR copies.
- if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1);
- return;
- }
-
- if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2);
- return;
- }
-
- if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4);
- return;
- }
-
- if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_8);
- return;
- }
-
- if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/3);
- return;
- }
-
- if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/3);
- return;
- }
-
- if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/4);
- return;
- }
-
- if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/4);
- return;
- }
-
- if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/5);
- return;
- }
-
- if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/6);
- return;
- }
-
- if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/7);
- return;
- }
-
- if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/8);
- return;
+ for (const auto &RegClass :
+ {RISCV::VRRegClass, RISCV::VRM2RegClass, RISCV::VRM4RegClass,
----------------
topperc wrote:
What is the type of this initializer list? Is it making copies of all of the register classes?
https://github.com/llvm/llvm-project/pull/84894
More information about the llvm-branch-commits
mailing list