[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

Craig Topper via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Tue Mar 12 16:23:23 PDT 2024


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@@ -14,12 +14,33 @@
 #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
 
 #define GET_REGINFO_HEADER
 #include "RISCVGenRegisterInfo.inc"
 
 namespace llvm {
 
+enum {
+  // The VLMul value of this RegisterClass.
+  VLMulShift = 0,
+  VLMulShiftMask = 0b111 << VLMulShift,
+
+  // The NF value of this RegisterClass.
+  NFShift = VLMulShift + 3,
+  NFShiftMask = 0b111 << NFShift,
+};
+
+/// \returns the LMUL for the register class.
+static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) {
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topperc wrote:

These should not be in llvm namespace. They should be in RISCV namespace

https://github.com/llvm/llvm-project/pull/84894


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