[llvm-branch-commits] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)
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llvm-branch-commits at lists.llvm.org
Tue Mar 12 03:40:31 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Wang Pengcheng (wangpc-pp)
<details>
<summary>Changes</summary>
This TSFlags was introduced by https://reviews.llvm.org/D108815.
We store VLMul/NF into TSFlags and add helpers to get them.
This can reduce some lines and I think there will be more usages.
---
Full diff: https://github.com/llvm/llvm-project/pull/84894.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+20-92)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.h (+22-1)
- (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.td (+15-11)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9fe5666d6a81f4..3e52583ec8ad82 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -295,18 +295,17 @@ static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI,
return false;
}
-void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, MCRegister DstReg,
- MCRegister SrcReg, bool KillSrc,
- RISCVII::VLMUL LMul, unsigned NF) const {
+void RISCVInstrInfo::copyPhysRegVector(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
+ const TargetRegisterClass &RegClass) const {
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
+ RISCVII::VLMUL LMul = getLMul(RegClass.TSFlags);
+ unsigned NF = getNF(RegClass.TSFlags);
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
- unsigned LMulVal;
- bool Fractional;
- std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
+ auto [LMulVal, Fractional] = RISCVVType::decodeVLMUL(LMul);
assert(!Fractional && "It is impossible be fractional lmul here.");
unsigned NumRegs = NF * LMulVal;
bool ReversedCopy =
@@ -489,90 +488,19 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
// VR->VR copies.
- if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1);
- return;
- }
-
- if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2);
- return;
- }
-
- if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4);
- return;
- }
-
- if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_8);
- return;
- }
-
- if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/3);
- return;
- }
-
- if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/3);
- return;
- }
-
- if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/4);
- return;
- }
-
- if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/4);
- return;
- }
-
- if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/5);
- return;
- }
-
- if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/6);
- return;
- }
-
- if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/7);
- return;
- }
-
- if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/8);
- return;
+ for (const auto &RegClass :
+ {RISCV::VRRegClass, RISCV::VRM2RegClass, RISCV::VRM4RegClass,
+ RISCV::VRM8RegClass, RISCV::VRN2M1RegClass, RISCV::VRN2M2RegClass,
+ RISCV::VRN2M4RegClass, RISCV::VRN3M1RegClass, RISCV::VRN3M2RegClass,
+ RISCV::VRN4M1RegClass, RISCV::VRN4M2RegClass, RISCV::VRN5M1RegClass,
+ RISCV::VRN6M1RegClass, RISCV::VRN7M1RegClass, RISCV::VRN8M1RegClass}) {
+ if (RegClass.contains(DstReg, SrcReg)) {
+ copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc,
+ getLMul(RegClass.TSFlags),
+ /*NF=*/
+ getNF(RegClass.TSFlags));
+ return;
+ }
}
llvm_unreachable("Impossible reg-to-reg copy");
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index dd049fca059719..7408245bdd5252 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -69,7 +69,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
void copyPhysRegVector(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
- RISCVII::VLMUL LMul, unsigned NF = 1) const;
+ const TargetRegisterClass &RegClass) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
bool KillSrc) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index 943c4f2627cf2f..ee2d79caa8fec6 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -14,12 +14,33 @@
#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#define GET_REGINFO_HEADER
#include "RISCVGenRegisterInfo.inc"
namespace llvm {
+enum {
+ // The VLMul value of this RegisterClass.
+ VLMulShift = 0,
+ VLMulShiftMask = 0b111 << VLMulShift,
+
+ // The NF value of this RegisterClass.
+ NFShift = VLMulShift + 3,
+ NFShiftMask = 0b111 << NFShift,
+};
+
+/// \returns the LMUL for the register class.
+static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) {
+ return static_cast<RISCVII::VLMUL>((TSFlags & VLMulShiftMask) >> VLMulShift);
+}
+
+/// \returns the NF for the register class.
+static inline unsigned getNF(uint64_t TSFlags) {
+ return static_cast<unsigned>((TSFlags & NFShiftMask) >> NFShift) + 1;
+}
+
struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
RISCVRegisterInfo(unsigned HwMode);
@@ -140,6 +161,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
return isVRRegClass(RC) || isVRNRegClass(RC);
}
};
-}
+} // namespace llvm
#endif
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 225b57554c1dc0..f2f815b0092c2d 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -483,7 +483,11 @@ class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
64, // The maximum supported ELEN is 64.
regList> {
int VLMul = Vlmul;
- int Size = !mul(Vlmul, 64);
+ int NF = 1;
+ int Size = !mul(Vlmul, NF, 64);
+
+ let TSFlags{2-0} = !logtwo(Vlmul);
+ let TSFlags{5-3} = !sub(NF, 1);
}
defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
@@ -532,9 +536,7 @@ def VRM8 : VReg<VM8VTs, (add V8M8, V16M8, V24M8, V0M8), 8>;
def VRM8NoV0 : VReg<VM8VTs, (sub VRM8, V0M8), 8>;
-def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
- let Size = 64;
-}
+def VMV0 : VReg<VMaskVTs, (add V0), 1>;
let RegInfos = XLenRI in {
def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>;
@@ -589,13 +591,15 @@ def VM : VReg<VMaskVTs, (add VR), 1>;
foreach m = LMULList in {
foreach nf = NFList<m>.L in {
- def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
- (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
- !mul(nf, m)>;
- def "VRN" # nf # "M" # m: VReg<[untyped],
- (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"),
- !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
- !mul(nf, m)>;
+ let NF = nf in {
+ def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
+ (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
+ m>;
+ def "VRN" # nf # "M" # m: VReg<[untyped],
+ (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"),
+ !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
+ m>;
+ }
}
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/84894
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