[llvm-branch-commits] [clang] release/18.x: [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100) (PR #84715)
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Sun Mar 10 20:55:39 PDT 2024
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/84715
Backport aeda1a6e800e 2f479b811274
Requested by: @SixWeining
>From a31f312f41f39aa6894ebcb23837dc76b052f6ad Mon Sep 17 00:00:00 2001
From: wanglei <wanglei at loongson.cn>
Date: Tue, 5 Mar 2024 19:44:28 +0800
Subject: [PATCH 1/2] [Clang][LoongArch] Precommit test for fix wrong return
value type of __iocsrrd_h. NFC
(cherry picked from commit aeda1a6e800e0dd6c91c0332b4db95094ad5b301)
---
clang/test/CodeGen/LoongArch/intrinsic-la32.c | 29 ++++++++++++++-----
clang/test/CodeGen/LoongArch/intrinsic-la64.c | 21 ++++++++++++--
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/clang/test/CodeGen/LoongArch/intrinsic-la32.c b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
index 93d54f511a9cd2..6a8d99880be399 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la32.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
@@ -169,8 +169,8 @@ unsigned int cpucfg(unsigned int a) {
// LA32-LABEL: @rdtime(
// LA32-NEXT: entry:
-// LA32-NEXT: [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
-// LA32-NEXT: [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// LA32-NEXT: [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc [[META2:![0-9]+]]
+// LA32-NEXT: [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc [[META3:![0-9]+]]
// LA32-NEXT: ret void
//
void rdtime() {
@@ -201,13 +201,28 @@ void loongarch_movgr2fcsr(int a) {
__builtin_loongarch_movgr2fcsr(1, a);
}
-// CHECK-LABEL: @cacop_w(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A:%.*]], i32 1024)
-// CHECK-NEXT: tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A]], i32 1024)
-// CHECK-NEXT: ret void
+// LA32-LABEL: @cacop_w(
+// LA32-NEXT: entry:
+// LA32-NEXT: tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A:%.*]], i32 1024)
+// LA32-NEXT: tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A]], i32 1024)
+// LA32-NEXT: ret void
//
void cacop_w(unsigned long int a) {
__cacop_w(1, a, 1024);
__builtin_loongarch_cacop_w(1, a, 1024);
}
+
+// LA32-LABEL: @iocsrrd_h_result(
+// LA32-NEXT: entry:
+// LA32-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A:%.*]])
+// LA32-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A]])
+// LA32-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 255
+// LA32-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
+// LA32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
+// LA32-NEXT: ret i16 [[CONV4]]
+//
+unsigned short iocsrrd_h_result(unsigned int a) {
+ unsigned short b = __iocsrrd_h(a);
+ unsigned short c = __builtin_loongarch_iocsrrd_h(a);
+ return b+c;
+}
diff --git a/clang/test/CodeGen/LoongArch/intrinsic-la64.c b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
index a740882eef5411..48b6a7a3d22704 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -387,7 +387,7 @@ unsigned int cpucfg(unsigned int a) {
// CHECK-LABEL: @rdtime_d(
// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect "rdtime.d $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect "rdtime.d $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc [[META2:![0-9]+]]
// CHECK-NEXT: ret void
//
void rdtime_d() {
@@ -396,8 +396,8 @@ void rdtime_d() {
// CHECK-LABEL: @rdtime(
// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
-// CHECK-NEXT: [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !4
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc [[META3:![0-9]+]]
+// CHECK-NEXT: [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc [[META4:![0-9]+]]
// CHECK-NEXT: ret void
//
void rdtime() {
@@ -427,3 +427,18 @@ void loongarch_movgr2fcsr(int a) {
__movgr2fcsr(1, a);
__builtin_loongarch_movgr2fcsr(1, a);
}
+
+// CHECK-LABEL: @iocsrrd_h_result(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A:%.*]])
+// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A]])
+// CHECK-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 255
+// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
+// CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK-NEXT: ret i16 [[CONV4]]
+//
+unsigned short iocsrrd_h_result(unsigned int a) {
+ unsigned short b = __iocsrrd_h(a);
+ unsigned short c = __builtin_loongarch_iocsrrd_h(a);
+ return b+c;
+}
>From 2e64d1828ad0e0d784aacaf46fd72ef63c0f845f Mon Sep 17 00:00:00 2001
From: wanglei <wanglei at loongson.cn>
Date: Wed, 6 Mar 2024 10:03:28 +0800
Subject: [PATCH 2/2] [Clang][LoongArch] Fix wrong return value type of
__iocsrrd_h (#84100)
relate:
https://gcc.gnu.org/pipermail/gcc-patches/2024-February/645016.html
(cherry picked from commit 2f479b811274fede36535e34ecb545ac22e399c3)
---
clang/lib/Headers/larchintrin.h | 2 +-
clang/test/CodeGen/LoongArch/intrinsic-la32.c | 8 ++++----
clang/test/CodeGen/LoongArch/intrinsic-la64.c | 8 ++++----
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/clang/lib/Headers/larchintrin.h b/clang/lib/Headers/larchintrin.h
index a613e5ca0e5ecd..f4218295919a0d 100644
--- a/clang/lib/Headers/larchintrin.h
+++ b/clang/lib/Headers/larchintrin.h
@@ -156,7 +156,7 @@ extern __inline unsigned char
return (unsigned char)__builtin_loongarch_iocsrrd_b((unsigned int)_1);
}
-extern __inline unsigned char
+extern __inline unsigned short
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
__iocsrrd_h(unsigned int _1) {
return (unsigned short)__builtin_loongarch_iocsrrd_h((unsigned int)_1);
diff --git a/clang/test/CodeGen/LoongArch/intrinsic-la32.c b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
index 6a8d99880be399..eb3f8cbe7ac4cc 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la32.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
@@ -215,11 +215,11 @@ void cacop_w(unsigned long int a) {
// LA32-LABEL: @iocsrrd_h_result(
// LA32-NEXT: entry:
// LA32-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A:%.*]])
+// LA32-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP0]] to i16
// LA32-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A]])
-// LA32-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 255
-// LA32-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
-// LA32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
-// LA32-NEXT: ret i16 [[CONV4]]
+// LA32-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
+// LA32-NEXT: [[CONV3:%.*]] = add i16 [[TMP2]], [[CONV_I]]
+// LA32-NEXT: ret i16 [[CONV3]]
//
unsigned short iocsrrd_h_result(unsigned int a) {
unsigned short b = __iocsrrd_h(a);
diff --git a/clang/test/CodeGen/LoongArch/intrinsic-la64.c b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
index 48b6a7a3d22704..50ec358f546ec0 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -431,11 +431,11 @@ void loongarch_movgr2fcsr(int a) {
// CHECK-LABEL: @iocsrrd_h_result(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A:%.*]])
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP0]] to i16
// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A]])
-// CHECK-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 255
-// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
-// CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK-NEXT: ret i16 [[CONV4]]
+// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
+// CHECK-NEXT: [[CONV3:%.*]] = add i16 [[TMP2]], [[CONV_I]]
+// CHECK-NEXT: ret i16 [[CONV3]]
//
unsigned short iocsrrd_h_result(unsigned int a) {
unsigned short b = __iocsrrd_h(a);
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