[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)
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Thu Mar 7 15:59:04 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Florian Mayer (fmayer)
<details>
<summary>Changes</summary>
Also be consistent about naming SP / FP.
This is to prepare for stack history buffer for memtag-stack
---
Full diff: https://github.com/llvm/llvm-project/pull/84404.diff
3 Files Affected:
- (modified) llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h (+5)
- (modified) llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp (+10-37)
- (modified) llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp (+34)
``````````diff
diff --git a/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h b/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
index eb00e6c4e856df..cbbb8ff34a59e6 100644
--- a/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
+++ b/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
@@ -17,6 +17,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/StackSafetyAnalysis.h"
+#include "llvm/IR/IRBuilder.h"
#include "llvm/Support/Alignment.h"
namespace llvm {
@@ -79,6 +80,10 @@ class StackInfoBuilder {
uint64_t getAllocaSizeInBytes(const AllocaInst &AI);
void alignAndPadAlloca(memtag::AllocaInfo &Info, llvm::Align Align);
+Value *readRegister(IRBuilder<> &IRB, StringRef Name);
+Value *getSP(IRBuilder<> &IRB);
+Value *getPC(const Triple &TargetTriple, IRBuilder<> &IRB);
+
} // namespace memtag
} // namespace llvm
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index 61d54b850374e1..e2cdca5b71f404 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -357,7 +357,6 @@ class HWAddressSanitizer {
bool instrumentStack(memtag::StackInfo &Info, Value *StackTag, Value *UARTag,
const DominatorTree &DT, const PostDominatorTree &PDT,
const LoopInfo &LI);
- Value *readRegister(IRBuilder<> &IRB, StringRef Name);
bool instrumentLandingPads(SmallVectorImpl<Instruction *> &RetVec);
Value *getNextTagWithCall(IRBuilder<> &IRB);
Value *getStackBaseTag(IRBuilder<> &IRB);
@@ -373,8 +372,7 @@ class HWAddressSanitizer {
void instrumentGlobal(GlobalVariable *GV, uint8_t Tag);
void instrumentGlobals();
- Value *getPC(IRBuilder<> &IRB);
- Value *getFP(IRBuilder<> &IRB);
+ Value *getCachedSP(IRBuilder<> &IRB);
Value *getFrameRecordInfo(IRBuilder<> &IRB);
void instrumentPersonalityFunctions();
@@ -1169,7 +1167,7 @@ Value *HWAddressSanitizer::getStackBaseTag(IRBuilder<> &IRB) {
// Extract some entropy from the stack pointer for the tags.
// Take bits 20..28 (ASLR entropy) and xor with bits 0..8 (these differ
// between functions).
- Value *StackPointerLong = getFP(IRB);
+ Value *StackPointerLong = getCachedSP(IRB);
Value *StackTag =
applyTagMask(IRB, IRB.CreateXor(StackPointerLong,
IRB.CreateLShr(StackPointerLong, 20)));
@@ -1186,7 +1184,7 @@ Value *HWAddressSanitizer::getAllocaTag(IRBuilder<> &IRB, Value *StackTag,
}
Value *HWAddressSanitizer::getUARTag(IRBuilder<> &IRB) {
- Value *StackPointerLong = getFP(IRB);
+ Value *StackPointerLong = getCachedSP(IRB);
Value *UARTag =
applyTagMask(IRB, IRB.CreateLShr(StackPointerLong, PointerTagShift));
@@ -1247,32 +1245,16 @@ Value *HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> &IRB, Type *Ty) {
return nullptr;
}
-Value *HWAddressSanitizer::getPC(IRBuilder<> &IRB) {
- if (TargetTriple.getArch() == Triple::aarch64)
- return readRegister(IRB, "pc");
- return IRB.CreatePtrToInt(IRB.GetInsertBlock()->getParent(), IntptrTy);
-}
-
-Value *HWAddressSanitizer::getFP(IRBuilder<> &IRB) {
- if (!CachedSP) {
- // FIXME: use addressofreturnaddress (but implement it in aarch64 backend
- // first).
- Function *F = IRB.GetInsertBlock()->getParent();
- Module *M = F->getParent();
- auto *GetStackPointerFn = Intrinsic::getDeclaration(
- M, Intrinsic::frameaddress,
- IRB.getPtrTy(M->getDataLayout().getAllocaAddrSpace()));
- CachedSP = IRB.CreatePtrToInt(
- IRB.CreateCall(GetStackPointerFn, {Constant::getNullValue(Int32Ty)}),
- IntptrTy);
- }
+Value *HWAddressSanitizer::getCachedSP(IRBuilder<> &IRB) {
+ if (!CachedSP)
+ CachedSP = memtag::getSP(IRB);
return CachedSP;
}
Value *HWAddressSanitizer::getFrameRecordInfo(IRBuilder<> &IRB) {
// Prepare ring buffer data.
- Value *PC = getPC(IRB);
- Value *SP = getFP(IRB);
+ Value *PC = memtag::getPC(TargetTriple, IRB);
+ Value *SP = getCachedSP(IRB);
// Mix SP and PC.
// Assumptions:
@@ -1366,23 +1348,14 @@ void HWAddressSanitizer::emitPrologue(IRBuilder<> &IRB, bool WithFrameRecord) {
}
}
-Value *HWAddressSanitizer::readRegister(IRBuilder<> &IRB, StringRef Name) {
- Module *M = IRB.GetInsertBlock()->getParent()->getParent();
- Function *ReadRegister =
- Intrinsic::getDeclaration(M, Intrinsic::read_register, IntptrTy);
- MDNode *MD = MDNode::get(*C, {MDString::get(*C, Name)});
- Value *Args[] = {MetadataAsValue::get(*C, MD)};
- return IRB.CreateCall(ReadRegister, Args);
-}
-
bool HWAddressSanitizer::instrumentLandingPads(
SmallVectorImpl<Instruction *> &LandingPadVec) {
for (auto *LP : LandingPadVec) {
IRBuilder<> IRB(LP->getNextNonDebugInstruction());
IRB.CreateCall(
HwasanHandleVfork,
- {readRegister(IRB, (TargetTriple.getArch() == Triple::x86_64) ? "rsp"
- : "sp")});
+ {memtag::readRegister(
+ IRB, (TargetTriple.getArch() == Triple::x86_64) ? "rsp" : "sp")});
}
return true;
}
diff --git a/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp b/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
index 2ffe89a2458405..08d98b97a46075 100644
--- a/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
+++ b/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
@@ -17,7 +17,9 @@
#include "llvm/Analysis/StackSafetyAnalysis.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/IR/BasicBlock.h"
+#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/TargetParser/Triple.h"
#include "llvm/Transforms/Utils/PromoteMemToReg.h"
namespace llvm {
@@ -237,5 +239,37 @@ void alignAndPadAlloca(memtag::AllocaInfo &Info, llvm::Align Alignment) {
Info.AI = NewAI;
}
+Value *readRegister(IRBuilder<> &IRB, StringRef Name) {
+ Module *M = IRB.GetInsertBlock()->getParent()->getParent();
+ Function *ReadRegister = Intrinsic::getDeclaration(
+ M, Intrinsic::read_register, IRB.getIntPtrTy(M->getDataLayout()));
+ MDNode *MD =
+ MDNode::get(M->getContext(), {MDString::get(M->getContext(), Name)});
+ Value *Args[] = {MetadataAsValue::get(M->getContext(), MD)};
+ return IRB.CreateCall(ReadRegister, Args);
+}
+
+Value *getPC(const Triple &TargetTriple, IRBuilder<> &IRB) {
+ Module *M = IRB.GetInsertBlock()->getParent()->getParent();
+ if (TargetTriple.getArch() == Triple::aarch64)
+ return memtag::readRegister(IRB, "pc");
+ return IRB.CreatePtrToInt(IRB.GetInsertBlock()->getParent(),
+ IRB.getIntPtrTy(M->getDataLayout()));
+}
+
+Value *getSP(IRBuilder<> &IRB) {
+ // FIXME: use addressofreturnaddress (but implement it in aarch64 backend
+ // first).
+ Function *F = IRB.GetInsertBlock()->getParent();
+ Module *M = F->getParent();
+ auto *GetStackPointerFn = Intrinsic::getDeclaration(
+ M, Intrinsic::frameaddress,
+ IRB.getPtrTy(M->getDataLayout().getAllocaAddrSpace()));
+ return IRB.CreatePtrToInt(
+ IRB.CreateCall(GetStackPointerFn,
+ {Constant::getNullValue(IRB.getInt32Ty())}),
+ IRB.getIntPtrTy(M->getDataLayout()));
+}
+
} // namespace memtag
} // namespace llvm
``````````
</details>
https://github.com/llvm/llvm-project/pull/84404
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