[llvm-branch-commits] [llvm] release/18.x: Convert many LivePhysRegs uses to LiveRegUnits (PR #84118)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Mar 7 11:07:19 PST 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/84118
>From 9adec28584b421aa4dad3a4af8e2d077ac76301c Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 5 Mar 2024 17:35:23 -0500
Subject: [PATCH] release/18.x: Convert many LivePhysRegs uses to LiveRegUnits
This only converts the instances where all that is needed is to change the variable type name.
Basically, anything that involves a function that LiveRegUnits does not directly have was skipped to play it safe. This is a subset of what was approved for main.
---
llvm/lib/CodeGen/ReachingDefAnalysis.cpp | 24 +++++++++----------
.../Target/AMDGPU/SIOptimizeExecMasking.cpp | 8 +++----
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 6 ++---
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 6 ++---
llvm/test/CodeGen/Thumb/PR35481.ll | 14 +++++------
5 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
index 61a668907be77d..07fa92889d8853 100644
--- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -6,10 +6,10 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/ADT/SmallSet.h"
-#include "llvm/ADT/SetOperations.h"
-#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/ReachingDefAnalysis.h"
+#include "llvm/ADT/SetOperations.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h"
@@ -421,9 +421,9 @@ void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB,
return;
VisitedBBs.insert(MBB);
- LivePhysRegs LiveRegs(*TRI);
+ LiveRegUnits LiveRegs(*TRI);
LiveRegs.addLiveOuts(*MBB);
- if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
+ if (LiveRegs.available(PhysReg))
return;
if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg))
@@ -469,11 +469,11 @@ MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI,
MCRegister PhysReg) const {
MachineBasicBlock *MBB = MI->getParent();
- LivePhysRegs LiveRegs(*TRI);
+ LiveRegUnits LiveRegs(*TRI);
LiveRegs.addLiveOuts(*MBB);
// Yes if the register is live out of the basic block.
- if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
+ if (!LiveRegs.available(PhysReg))
return true;
// Walk backwards through the block to see if the register is live at some
@@ -481,7 +481,7 @@ bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI,
for (MachineInstr &Last :
instructionsWithoutDebug(MBB->instr_rbegin(), MBB->instr_rend())) {
LiveRegs.stepBackward(Last);
- if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
+ if (!LiveRegs.available(PhysReg))
return InstIds.lookup(&Last) > InstIds.lookup(MI);
}
return false;
@@ -504,9 +504,9 @@ bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI,
bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
MCRegister PhysReg) const {
MachineBasicBlock *MBB = MI->getParent();
- LivePhysRegs LiveRegs(*TRI);
+ LiveRegUnits LiveRegs(*TRI);
LiveRegs.addLiveOuts(*MBB);
- if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
+ if (LiveRegs.available(PhysReg))
return false;
auto Last = MBB->getLastNonDebugInstr();
@@ -525,9 +525,9 @@ bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
MachineInstr *
ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB,
MCRegister PhysReg) const {
- LivePhysRegs LiveRegs(*TRI);
+ LiveRegUnits LiveRegs(*TRI);
LiveRegs.addLiveOuts(*MBB);
- if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
+ if (LiveRegs.available(PhysReg))
return nullptr;
auto Last = MBB->getLastNonDebugInstr();
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index e3f54d01eb22a2..3c60459e54e8fa 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -11,7 +11,7 @@
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIRegisterInfo.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -313,7 +313,7 @@ MachineBasicBlock::reverse_iterator SIOptimizeExecMasking::findExecCopy(
return E;
}
-// XXX - Seems LivePhysRegs doesn't work correctly since it will incorrectly
+// XXX - Seems LiveRegUnits doesn't work correctly since it will incorrectly
// report the register as unavailable because a super-register with a lane mask
// is unavailable.
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) {
@@ -383,7 +383,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
MCRegister Reg,
bool UseLiveOuts,
bool IgnoreStart) const {
- LivePhysRegs LR(*TRI);
+ LiveRegUnits LR(*TRI);
if (UseLiveOuts)
LR.addLiveOuts(*Stop.getParent());
@@ -396,7 +396,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
LR.stepBackward(*A);
}
- return !LR.available(*MRI, Reg);
+ return !LR.available(Reg) || MRI->isReserved(Reg);
}
// Determine if a register Reg is not re-defined and still in use
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index ed9d30c3c3ab90..874fc0a9d402a0 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -31,7 +31,7 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -109,7 +109,7 @@ namespace {
const ARMSubtarget *STI;
const TargetLowering *TL;
ARMFunctionInfo *AFI;
- LivePhysRegs LiveRegs;
+ LiveRegUnits LiveRegs;
RegisterClassInfo RegClassInfo;
MachineBasicBlock::const_iterator LiveRegPos;
bool LiveRegsValid;
@@ -589,7 +589,7 @@ unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
}
for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
- if (LiveRegs.available(MF->getRegInfo(), Reg))
+ if (LiveRegs.available(Reg) && !MF->getRegInfo().isReserved(Reg))
return Reg;
return 0;
}
diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index 0f4ece64bff532..a8cf036f363cdd 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -612,11 +612,11 @@ bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
const BitVector &PopFriendly,
- const LivePhysRegs &UsedRegs, unsigned &PopReg,
+ const LiveRegUnits &UsedRegs, unsigned &PopReg,
unsigned &TmpReg, MachineRegisterInfo &MRI) {
PopReg = TmpReg = 0;
for (auto Reg : GPRsNoLRSP.set_bits()) {
- if (UsedRegs.available(MRI, Reg)) {
+ if (UsedRegs.available(Reg)) {
// Remember the first pop-friendly register and exit.
if (PopFriendly.test(Reg)) {
PopReg = Reg;
@@ -684,7 +684,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
// Look for a temporary register to use.
// First, compute the liveness information.
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
- LivePhysRegs UsedRegs(TRI);
+ LiveRegUnits UsedRegs(TRI);
UsedRegs.addLiveOuts(MBB);
// The semantic of pristines changed recently and now,
// the callee-saved registers that are touched in the function
diff --git a/llvm/test/CodeGen/Thumb/PR35481.ll b/llvm/test/CodeGen/Thumb/PR35481.ll
index ad3215ecb94952..e48d1547782caf 100644
--- a/llvm/test/CodeGen/Thumb/PR35481.ll
+++ b/llvm/test/CodeGen/Thumb/PR35481.ll
@@ -18,11 +18,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
; CHECK-V4T-NEXT: movs r2, #3
; CHECK-V4T-NEXT: movs r3, #4
; CHECK-V4T-NEXT: bl g
+; CHECK-V4T-NEXT: ldr r7, [sp, #4]
+; CHECK-V4T-NEXT: mov lr, r7
; CHECK-V4T-NEXT: pop {r7}
-; CHECK-V4T-NEXT: mov r12, r0
-; CHECK-V4T-NEXT: pop {r0}
-; CHECK-V4T-NEXT: mov lr, r0
-; CHECK-V4T-NEXT: mov r0, r12
+; CHECK-V4T-NEXT: add sp, #4
; CHECK-V4T-NEXT: bx lr
;
; CHECK-V8M-LABEL: f:
@@ -36,11 +35,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
; CHECK-V8M-NEXT: movs r1, #2
; CHECK-V8M-NEXT: movs r2, #3
; CHECK-V8M-NEXT: movs r3, #4
+; CHECK-V8M-NEXT: ldr r7, [sp, #4]
+; CHECK-V8M-NEXT: mov lr, r7
; CHECK-V8M-NEXT: pop {r7}
-; CHECK-V8M-NEXT: mov r12, r0
-; CHECK-V8M-NEXT: pop {r0}
-; CHECK-V8M-NEXT: mov lr, r0
-; CHECK-V8M-NEXT: mov r0, r12
+; CHECK-V8M-NEXT: add sp, #4
; CHECK-V8M-NEXT: b g
entry:
%call = tail call i32 @h(i32 1)
More information about the llvm-branch-commits
mailing list