[llvm-branch-commits] [llvm] [llvm-exegesis] Add additional validation counters (PR #76788)
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Wed Jan 3 00:30:25 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Aiden Grossman (boomanaiden154)
<details>
<summary>Changes</summary>
This patch adds support for additional types of validation counters and also adds mappings between these new validation counter types and physical counters on the hardware for microarchitectures that I have the ability to test on.
---
Full diff: https://github.com/llvm/llvm-project/pull/76788.diff
5 Files Affected:
- (modified) llvm/include/llvm/Target/TargetPfmCounters.td (+7)
- (modified) llvm/lib/Target/X86/X86PfmCounters.td (+36-6)
- (modified) llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp (+24)
- (modified) llvm/tools/llvm-exegesis/lib/BenchmarkResult.h (+6)
- (modified) llvm/tools/llvm-exegesis/llvm-exegesis.cpp (+15-3)
``````````diff
diff --git a/llvm/include/llvm/Target/TargetPfmCounters.td b/llvm/include/llvm/Target/TargetPfmCounters.td
index d162327afea2cf..0bfefd5d31211e 100644
--- a/llvm/include/llvm/Target/TargetPfmCounters.td
+++ b/llvm/include/llvm/Target/TargetPfmCounters.td
@@ -33,6 +33,13 @@ class ValidationEvent <int event_number> {
}
def InstructionRetired : ValidationEvent<0>;
+def L1DCacheLoadMiss : ValidationEvent<1>;
+def L1DCacheStoreMiss : ValidationEvent<2>;
+def L1ICacheLoadMiss : ValidationEvent<3>;
+def DataTLBLoadMiss : ValidationEvent<4>;
+def DataTLBStoreMiss : ValidationEvent<5>;
+def InstructionTLBLoadMiss : ValidationEvent<6>;
+
// Validation counters can be tied to a specific event
class PfmValidationCounter<ValidationEvent event_type, string counter>
diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td
index 52c86b1f74c1cb..4403b9845be920 100644
--- a/llvm/lib/Target/X86/X86PfmCounters.td
+++ b/llvm/lib/Target/X86/X86PfmCounters.td
@@ -121,7 +121,12 @@ def HaswellPfmCounters : ProcPfmCounters {
PfmIssueCounter<"HWPort7", "uops_executed_port:port_7">
];
let ValidationCounters = [
- PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">
+ PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">,
+ PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_UOPS_RETIRED:L1_MISS">,
+ PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
+ PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">,
+ PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">,
+ PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK">
];
}
def : PfmCountersBinding<"haswell", HaswellPfmCounters>;
@@ -140,7 +145,12 @@ def BroadwellPfmCounters : ProcPfmCounters {
PfmIssueCounter<"BWPort7", "uops_executed_port:port_7">
];
let ValidationCounters = [
- PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">
+ PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">,
+ PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_UOPS_RETIRED:L1_MISS">,
+ PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
+ PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">,
+ PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">,
+ PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK">
];
}
def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>;
@@ -159,7 +169,12 @@ def SkylakeClientPfmCounters : ProcPfmCounters {
PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7">
];
let ValidationCounters = [
- PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">
+ PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">,
+ PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_RETIRED:L1_MISS">,
+ PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
+ PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">,
+ PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">,
+ PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK">
];
}
def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>;
@@ -178,7 +193,12 @@ def SkylakeServerPfmCounters : ProcPfmCounters {
PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7">
];
let ValidationCounters = [
- PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">
+ PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">,
+ PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_RETIRED:L1_MISS">,
+ PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
+ PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">,
+ PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">,
+ PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK">
];
}
def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>;
@@ -297,7 +317,12 @@ def ZnVer2PfmCounters : ProcPfmCounters {
PfmIssueCounter<"Zn2Divider", "div_op_count">
];
let ValidationCounters = [
- PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">
+ PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,
+ PfmValidationCounter<L1DCacheLoadMiss, "L1-DCACHE-LOAD-MISSES">,
+ PfmValidationCounter<L1DCacheStoreMiss, "L1-DCACHE-STORE-MISSES">,
+ PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
+ PfmValidationCounter<DataTLBLoadMiss, "DTLB-LOAD-MISSES">,
+ PfmValidationCounter<InstructionTLBLoadMiss, "ITLB-LOAD-MISSES">
];
}
def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>;
@@ -313,7 +338,12 @@ def ZnVer3PfmCounters : ProcPfmCounters {
PfmIssueCounter<"Zn3Divider", "div_op_count">
];
let ValidationCounters = [
- PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">
+ PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,
+ PfmValidationCounter<L1DCacheLoadMiss, "L1-DCACHE-LOAD-MISSES">,
+ PfmValidationCounter<L1DCacheStoreMiss, "L1-DCACHE-STORE-MISSES">,
+ PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">,
+ PfmValidationCounter<DataTLBLoadMiss, "DTLB-LOAD-MISSES">,
+ PfmValidationCounter<InstructionTLBLoadMiss, "ITLB-LOAD-MISSES">
];
}
def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>;
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
index d3f69beb19c46f..bec96c13672782 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
@@ -197,12 +197,36 @@ const char *validationEventToString(exegesis::ValidationEvent VE) {
switch (VE) {
case exegesis::ValidationEvent::InstructionRetired:
return "instructions-retired";
+ case exegesis::ValidationEvent::L1DCacheLoadMiss:
+ return "l1d-cache-load-misses";
+ case exegesis::ValidationEvent::L1DCacheStoreMiss:
+ return "l1d-cache-store-misses";
+ case exegesis::ValidationEvent::L1ICacheLoadMiss:
+ return "l1i-cache-load-misses";
+ case exegesis::ValidationEvent::DataTLBLoadMiss:
+ return "data-tlb-load-misses";
+ case exegesis::ValidationEvent::DataTLBStoreMiss:
+ return "data-tlb-store-misses";
+ case exegesis::ValidationEvent::InstructionTLBLoadMiss:
+ return "instruction-tlb-load-misses";
}
}
Expected<exegesis::ValidationEvent> stringToValidationEvent(StringRef Input) {
if (Input == "instructions-retired")
return exegesis::ValidationEvent::InstructionRetired;
+ else if (Input == "l1d-cache-load-misses")
+ return exegesis::ValidationEvent::L1DCacheLoadMiss;
+ else if (Input == "l1d-cache-store-misses")
+ return exegesis::ValidationEvent::L1DCacheStoreMiss;
+ else if (Input == "l1i-cache-load-misses")
+ return exegesis::ValidationEvent::L1ICacheLoadMiss;
+ else if (Input == "data-tlb-load-misses")
+ return exegesis::ValidationEvent::DataTLBLoadMiss;
+ else if (Input == "data-tlb-store-misses")
+ return exegesis::ValidationEvent::DataTLBStoreMiss;
+ else if (Input == "instruction-tlb-load-misses")
+ return exegesis::ValidationEvent::InstructionTLBLoadMiss;
else
return make_error<StringError>("Invalid validation event string",
errc::invalid_argument);
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
index 9fc5d851b29abb..56d907cea0f78a 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
@@ -34,6 +34,12 @@ namespace exegesis {
enum ValidationEvent {
InstructionRetired,
+ L1DCacheLoadMiss,
+ L1DCacheStoreMiss,
+ L1ICacheLoadMiss,
+ DataTLBLoadMiss,
+ DataTLBStoreMiss,
+ InstructionTLBLoadMiss
};
enum class BenchmarkPhaseSelectorE {
diff --git a/llvm/tools/llvm-exegesis/llvm-exegesis.cpp b/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
index 29617532d27d86..fc19c052c35abc 100644
--- a/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
+++ b/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
@@ -274,9 +274,21 @@ static cl::list<ValidationEvent> ValidationCounters(
"The name of a validation counter to run concurrently with the main "
"counter to validate benchmarking assumptions"),
cl::CommaSeparated, cl::cat(BenchmarkOptions),
- cl::values(clEnumValN(ValidationEvent::InstructionRetired,
- "instructions-retired",
- "Count retired instructions")));
+ cl::values(
+ clEnumValN(ValidationEvent::InstructionRetired, "instructions-retired",
+ "Count retired instructions"),
+ clEnumValN(ValidationEvent::L1DCacheLoadMiss, "l1d-cache-load-misses",
+ "Count L1D load cache misses"),
+ clEnumValN(ValidationEvent::L1DCacheStoreMiss, "l1d-cache-store-misses",
+ "Count L1D store cache misses"),
+ clEnumValN(ValidationEvent::L1ICacheLoadMiss, "l1i-cache-load-misses",
+ "Count L1I load cache misses"),
+ clEnumValN(ValidationEvent::DataTLBLoadMiss, "data-tlb-load-misses",
+ "Count DTLB load misses"),
+ clEnumValN(ValidationEvent::DataTLBStoreMiss, "data-tlb-store-misses",
+ "Count DTLB store misses"),
+ clEnumValN(ValidationEvent::InstructionTLBLoadMiss,
+ "instruction-tlb-load-misses", "Count ITLB load misses")));
static ExitOnError ExitOnErr("llvm-exegesis error: ");
``````````
</details>
https://github.com/llvm/llvm-project/pull/76788
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