[llvm-branch-commits] [llvm] PR for llvm/llvm-project#80877 (PR #80878)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Feb 6 15:49:48 PST 2024
https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/80878
>From 36cecd98cfd006e2b3b044e1433a8914916c98b9 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Tue, 6 Feb 2024 09:23:33 -0800
Subject: [PATCH] [MIPS] Use generic isBlockOnlyReachableByFallthrough (#80799)
FastISel may create a redundant BGTZ terminal which fallthroughes.
```
BGTZ %2:gpr32, %bb.1, implicit-def $at
bb.1.bb1:
; predecessors: %bb.0
```
The `!I->isBarrier()` check in
MipsAsmPrinter::isBlockOnlyReachableByFallthrough
will incorrectly not print a label, leading to a `Undefined temporary
symbol `
error when we try assembling the output assembly file. See the updated
`Fast-ISel/pr40325.ll` and
https://github.com/rust-lang/rust/issues/108835
In addition, the `SwitchInst` condition is too conservative and prints
many unneeded labels (see the updated tests).
Just use the generic isBlockOnlyReachableByFallthrough, updated by
commit 1995b9fead62f2f6c0ad217bd00ce3184f741fdb for SPARC, which also
handles MIPS.
(cherry picked from commit 6b2fd7aed66d592738f26c76caa8fff95e168598)
---
llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 39 -------------------
llvm/lib/Target/Mips/MipsAsmPrinter.h | 2 -
llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll | 2 +-
.../GlobalISel/llvm-ir/jump_table_and_brjt.ll | 8 ++--
.../unsafe-in-forbidden-slot.ll | 4 +-
.../Mips/indirect-jump-hazard/jumptables.ll | 16 ++++----
llvm/test/CodeGen/Mips/jump-table-mul.ll | 2 +-
llvm/test/CodeGen/Mips/pseudo-jump-fill.ll | 2 +-
8 files changed, 17 insertions(+), 58 deletions(-)
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 718844bc36ff93..66b2b0de8d52a3 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -471,45 +471,6 @@ void MipsAsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) {
TS.emitDirectiveInsn();
}
-/// isBlockOnlyReachableByFallthough - Return true if the basic block has
-/// exactly one predecessor and the control transfer mechanism between
-/// the predecessor and this block is a fall-through.
-bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
- MBB) const {
- // The predecessor has to be immediately before this block.
- const MachineBasicBlock *Pred = *MBB->pred_begin();
-
- // If the predecessor is a switch statement, assume a jump table
- // implementation, so it is not a fall through.
- if (const BasicBlock *bb = Pred->getBasicBlock())
- if (isa<SwitchInst>(bb->getTerminator()))
- return false;
-
- // If this is a landing pad, it isn't a fall through. If it has no preds,
- // then nothing falls through to it.
- if (MBB->isEHPad() || MBB->pred_empty())
- return false;
-
- // If there isn't exactly one predecessor, it can't be a fall through.
- if (MBB->pred_size() != 1)
- return false;
-
- // The predecessor has to be immediately before this block.
- if (!Pred->isLayoutSuccessor(MBB))
- return false;
-
- // If the block is completely empty, then it definitely does fall through.
- if (Pred->empty())
- return true;
-
- // Otherwise, check the last instruction.
- // Check if the last terminator is an unconditional branch.
- MachineBasicBlock::const_iterator I = Pred->end();
- while (I != Pred->begin() && !(--I)->isTerminator()) ;
-
- return !I->isBarrier();
-}
-
// Print out an operand for an inline asm expression.
bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
const char *ExtraCode, raw_ostream &O) {
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h
index 64424b181504a7..0b55089385d79d 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.h
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h
@@ -142,8 +142,6 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter {
void emitFunctionBodyStart() override;
void emitFunctionBodyEnd() override;
void emitBasicBlockEnd(const MachineBasicBlock &MBB) override;
- bool isBlockOnlyReachableByFallthrough(
- const MachineBasicBlock* MBB) const override;
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
const char *ExtraCode, raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll b/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
index 9e64d7b2fa039b..c276515920d52a 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
@@ -11,7 +11,7 @@ define void @test(i32 %x, ptr %p) nounwind {
; CHECK-NEXT: andi $1, $4, 1
; CHECK-NEXT: bgtz $1, $BB0_1
; CHECK-NEXT: nop
-; CHECK-NEXT: # %bb.1: # %foo
+; CHECK-NEXT: $BB0_1: # %foo
; CHECK-NEXT: jr $ra
; CHECK-NEXT: nop
%y = and i32 %x, 1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
index 4c10fedaa4a884..74765ff0e8f106 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
@@ -25,7 +25,7 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: sltu $1, $1, $2
; MIPS32-NEXT: bnez $1, $BB0_6
; MIPS32-NEXT: nop
-; MIPS32-NEXT: $BB0_1: # %entry
+; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lui $1, %hi($JTI0_0)
; MIPS32-NEXT: sll $2, $2, 2
@@ -65,7 +65,7 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: sltu $1, $1, $2
; MIPS32-NEXT: bnez $1, $BB0_13
; MIPS32-NEXT: nop
-; MIPS32-NEXT: $BB0_8: # %sw.epilog
+; MIPS32-NEXT: # %bb.8: # %sw.epilog
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lui $1, %hi($JTI0_1)
; MIPS32-NEXT: sll $2, $2, 2
@@ -125,7 +125,7 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32_PIC-NEXT: sltu $1, $1, $2
; MIPS32_PIC-NEXT: bnez $1, $BB0_6
; MIPS32_PIC-NEXT: nop
-; MIPS32_PIC-NEXT: $BB0_1: # %entry
+; MIPS32_PIC-NEXT: # %bb.1: # %entry
; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $3, 36($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $1, %got($JTI0_0)($2)
@@ -167,7 +167,7 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32_PIC-NEXT: sltu $1, $1, $2
; MIPS32_PIC-NEXT: bnez $1, $BB0_13
; MIPS32_PIC-NEXT: nop
-; MIPS32_PIC-NEXT: $BB0_8: # %sw.epilog
+; MIPS32_PIC-NEXT: # %bb.8: # %sw.epilog
; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $1, %got($JTI0_1)($2)
diff --git a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
index cbd8b2370ac969..de61515cff9bcb 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
@@ -18,7 +18,7 @@ sw.bb: ; preds = %entry
br label %sw.epilog
; CHECK: beqzc
; CHECK-NEXT: nop
-; CHECK-NEXT: .LBB
+; CHECK-NEXT: # %bb.1
; CHECK-NEXT: j
sw.bb1: ; preds = %entry, %entry
@@ -26,7 +26,7 @@ sw.bb1: ; preds = %entry, %entry
br label %sw.epilog
; CHECK: bnezc
; CHECK-NEXT: nop
-; CHECK-NEXT: .LBB
+; CHECK-NEXT: # %bb.3
; CHECK-NEXT: j
sw.epilog: ; preds = %entry, %sw.bb1, %sw.bb
diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
index 1ce46cfa07cf87..634216027ef6bb 100644
--- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
+++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
@@ -42,7 +42,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
; MIPS32R2-NEXT: sltiu $1, $4, 7
; MIPS32R2-NEXT: beqz $1, $BB0_6
; MIPS32R2-NEXT: sw $4, 4($sp)
-; MIPS32R2-NEXT: $BB0_1: # %entry
+; MIPS32R2-NEXT: # %bb.1: # %entry
; MIPS32R2-NEXT: sll $1, $4, 2
; MIPS32R2-NEXT: lui $2, %hi($JTI0_0)
; MIPS32R2-NEXT: addu $1, $1, $2
@@ -100,7 +100,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
; MIPS32R6-NEXT: sltiu $1, $4, 7
; MIPS32R6-NEXT: beqz $1, $BB0_6
; MIPS32R6-NEXT: sw $4, 4($sp)
-; MIPS32R6-NEXT: $BB0_1: # %entry
+; MIPS32R6-NEXT: # %bb.1: # %entry
; MIPS32R6-NEXT: sll $1, $4, 2
; MIPS32R6-NEXT: lui $2, %hi($JTI0_0)
; MIPS32R6-NEXT: addu $1, $1, $2
@@ -159,7 +159,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
; MIPS64R2-NEXT: sltiu $1, $2, 7
; MIPS64R2-NEXT: beqz $1, .LBB0_6
; MIPS64R2-NEXT: sw $4, 4($sp)
-; MIPS64R2-NEXT: .LBB0_1: # %entry
+; MIPS64R2-NEXT: # %bb.1: # %entry
; MIPS64R2-NEXT: dsll $1, $2, 3
; MIPS64R2-NEXT: lui $2, %highest(.LJTI0_0)
; MIPS64R2-NEXT: daddiu $2, $2, %higher(.LJTI0_0)
@@ -254,7 +254,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
; MIPS64R6-NEXT: sltiu $1, $2, 7
; MIPS64R6-NEXT: beqz $1, .LBB0_6
; MIPS64R6-NEXT: sw $4, 4($sp)
-; MIPS64R6-NEXT: .LBB0_1: # %entry
+; MIPS64R6-NEXT: # %bb.1: # %entry
; MIPS64R6-NEXT: dsll $1, $2, 3
; MIPS64R6-NEXT: lui $2, %highest(.LJTI0_0)
; MIPS64R6-NEXT: daddiu $2, $2, %higher(.LJTI0_0)
@@ -351,7 +351,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
; PIC-MIPS32R2-NEXT: sltiu $1, $4, 7
; PIC-MIPS32R2-NEXT: beqz $1, $BB0_6
; PIC-MIPS32R2-NEXT: sw $4, 4($sp)
-; PIC-MIPS32R2-NEXT: $BB0_1: # %entry
+; PIC-MIPS32R2-NEXT: # %bb.1: # %entry
; PIC-MIPS32R2-NEXT: sll $1, $4, 2
; PIC-MIPS32R2-NEXT: lw $3, %got($JTI0_0)($2)
; PIC-MIPS32R2-NEXT: addu $1, $1, $3
@@ -413,7 +413,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
; PIC-MIPS32R6-NEXT: sltiu $1, $4, 7
; PIC-MIPS32R6-NEXT: beqz $1, $BB0_6
; PIC-MIPS32R6-NEXT: sw $4, 4($sp)
-; PIC-MIPS32R6-NEXT: $BB0_1: # %entry
+; PIC-MIPS32R6-NEXT: # %bb.1: # %entry
; PIC-MIPS32R6-NEXT: sll $1, $4, 2
; PIC-MIPS32R6-NEXT: lw $3, %got($JTI0_0)($2)
; PIC-MIPS32R6-NEXT: addu $1, $1, $3
@@ -476,7 +476,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
; PIC-MIPS64R2-NEXT: sltiu $1, $3, 7
; PIC-MIPS64R2-NEXT: beqz $1, .LBB0_6
; PIC-MIPS64R2-NEXT: sw $4, 4($sp)
-; PIC-MIPS64R2-NEXT: .LBB0_1: # %entry
+; PIC-MIPS64R2-NEXT: # %bb.1: # %entry
; PIC-MIPS64R2-NEXT: dsll $1, $3, 3
; PIC-MIPS64R2-NEXT: ld $3, %got_page(.LJTI0_0)($2)
; PIC-MIPS64R2-NEXT: daddu $1, $1, $3
@@ -539,7 +539,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
; PIC-MIPS64R6-NEXT: sltiu $1, $3, 7
; PIC-MIPS64R6-NEXT: beqz $1, .LBB0_6
; PIC-MIPS64R6-NEXT: sw $4, 4($sp)
-; PIC-MIPS64R6-NEXT: .LBB0_1: # %entry
+; PIC-MIPS64R6-NEXT: # %bb.1: # %entry
; PIC-MIPS64R6-NEXT: dsll $1, $3, 3
; PIC-MIPS64R6-NEXT: ld $3, %got_page(.LJTI0_0)($2)
; PIC-MIPS64R6-NEXT: daddu $1, $1, $3
diff --git a/llvm/test/CodeGen/Mips/jump-table-mul.ll b/llvm/test/CodeGen/Mips/jump-table-mul.ll
index 22f41f53d154bf..cca6080a07544c 100644
--- a/llvm/test/CodeGen/Mips/jump-table-mul.ll
+++ b/llvm/test/CodeGen/Mips/jump-table-mul.ll
@@ -10,7 +10,7 @@ define i64 @test(i64 %arg) {
; CHECK-NEXT: sltiu $1, $4, 11
; CHECK-NEXT: beqz $1, .LBB0_4
; CHECK-NEXT: nop
-; CHECK-NEXT: .LBB0_1: # %entry
+; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test)))
; CHECK-NEXT: dsll $2, $4, 3
; CHECK-NEXT: ld $3, %got_page(.LJTI0_0)($1)
diff --git a/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll b/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
index afb79e55f4f90b..5d7cdbc0b69edf 100644
--- a/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
+++ b/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
@@ -14,7 +14,7 @@ define i32 @test(i32 signext %x, i32 signext %c) {
; CHECK-NEXT: sltiu $1, $5, 4
; CHECK-NEXT: beqz $1, $BB0_6
; CHECK-NEXT: addu $3, $2, $25
-; CHECK-NEXT: $BB0_1: # %entry
+; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li16 $2, 0
; CHECK-NEXT: sll16 $5, $5, 2
; CHECK-NEXT: lw $6, %got($JTI0_0)($3)
More information about the llvm-branch-commits
mailing list