[llvm-branch-commits] [llvm] 69b3baf - [DAG] WidenVectorOperand - add basic handling for *_EXTEND_VECTOR_INREG nodes

[Tobias Hieta via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2023-11-13T11:05:25+01:00
New Revision: 69b3baf9b87eabfa307d8f74f7d0eea9df28cd5a

URL: https://github.com/llvm/llvm-project/commit/69b3baf9b87eabfa307d8f74f7d0eea9df28cd5a
DIFF: https://github.com/llvm/llvm-project/commit/69b3baf9b87eabfa307d8f74f7d0eea9df28cd5a.diff

LOG: [DAG] WidenVectorOperand - add basic handling for *_EXTEND_VECTOR_INREG nodes

Fixes Issue #70208

(cherry picked from commit c9c9bf0f20fd820b86fac35113bbd8049ff4e72a)

Added: 
    llvm/test/CodeGen/PowerPC/pr70208.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index db8f61eee6062ca..ad70655de349699 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -1000,6 +1000,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
   SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
   SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
   SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
+  SDValue WidenVecOp_EXTEND_VECTOR_INREG(SDNode *N);
   SDValue WidenVecOp_STORE(SDNode* N);
   SDValue WidenVecOp_VP_STORE(SDNode *N, unsigned OpNo);
   SDValue WidenVecOp_VP_STRIDED_STORE(SDNode *N, unsigned OpNo);

diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 8c117c1c74dc785..9c1839f2576e366 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -5946,6 +5946,11 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
   case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
     Res = WidenVecOp_VP_STRIDED_STORE(N, OpNo);
     break;
+  case ISD::ANY_EXTEND_VECTOR_INREG:
+  case ISD::SIGN_EXTEND_VECTOR_INREG:
+  case ISD::ZERO_EXTEND_VECTOR_INREG:
+    Res = WidenVecOp_EXTEND_VECTOR_INREG(N);
+    break;
   case ISD::MSTORE:             Res = WidenVecOp_MSTORE(N, OpNo); break;
   case ISD::MGATHER:            Res = WidenVecOp_MGATHER(N, OpNo); break;
   case ISD::MSCATTER:           Res = WidenVecOp_MSCATTER(N, OpNo); break;
@@ -6338,6 +6343,11 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
                      N->getValueType(0), InOp, N->getOperand(1));
 }
 
+SDValue DAGTypeLegalizer::WidenVecOp_EXTEND_VECTOR_INREG(SDNode *N) {
+  SDValue InOp = GetWidenedVector(N->getOperand(0));
+  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), InOp);
+}
+
 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
   // We have to widen the value, but we want only to store the original
   // vector type.

diff  --git a/llvm/test/CodeGen/PowerPC/pr70208.ll b/llvm/test/CodeGen/PowerPC/pr70208.ll
new file mode 100644
index 000000000000000..3a8d0eb00061138
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr70208.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -verify-machineinstrs -mtriple=ppc64le-unknown-linux-gnu < %s | FileCheck %s
+
+define <4 x i64> @widget(<8 x i16> %call) {
+; CHECK-LABEL: widget:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addis 3, 2, .LCPI0_0 at toc@ha
+; CHECK-NEXT:    addis 4, 2, .LCPI0_1 at toc@ha
+; CHECK-NEXT:    xxlxor 37, 37, 37
+; CHECK-NEXT:    addi 3, 3, .LCPI0_0 at toc@l
+; CHECK-NEXT:    lxvd2x 0, 0, 3
+; CHECK-NEXT:    addi 3, 4, .LCPI0_1 at toc@l
+; CHECK-NEXT:    lxvd2x 1, 0, 3
+; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    xxswapd 32, 1
+; CHECK-NEXT:    vperm 4, 5, 2, 3
+; CHECK-NEXT:    vperm 3, 5, 2, 0
+; CHECK-NEXT:    vmr 2, 4
+; CHECK-NEXT:    blr
+  %bitcast = bitcast <8 x i16> %call to <16 x i8>
+  %shufflevector = shufflevector <16 x i8> <i8 poison, i8 poison, i8 0, i8 0, i8 poison, i8 poison, i8 0, i8 0, i8 poison, i8 poison, i8 0, i8 0, i8 poison, i8 poison, i8 0, i8 0>, <16 x i8> %bitcast, <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 6, i32 7, i32 20, i32 21, i32 10, i32 11, i32 22, i32 23, i32 14, i32 15>
+  %bitcast1 = bitcast <16 x i8> %shufflevector to <4 x i32>
+  %zext = zext <4 x i32> %bitcast1 to <4 x i64>
+  ret <4 x i64> %zext
+}