[llvm-branch-commits] [llvm] 1de314f - [AArch64] Correct the regtype of indexed fmlal

[Tobias Hieta via llvm-branch-commits]

Author: David Green
Date: 2023-07-27T15:33:56+02:00
New Revision: 1de314f828fd502440eb0466503a8397005f5e36

URL: https://github.com/llvm/llvm-project/commit/1de314f828fd502440eb0466503a8397005f5e36
DIFF: https://github.com/llvm/llvm-project/commit/1de314f828fd502440eb0466503a8397005f5e36.diff

LOG: [AArch64] Correct the regtype of indexed fmlal

The indexed fmlal should use a low numbered register for the index operand,
which this fixes by making it V128_lo.

Fixes 64104

Differential Revision: https://reviews.llvm.org/D156296

(cherry picked from commit 509cb334699a2360f2d87f184bc0f56f742c6fc3)

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrFormats.td
    llvm/test/CodeGen/AArch64/fmlal-loreg.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index cd2b9df27a240f..d39fd69f9e0ee4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -8440,12 +8440,12 @@ class BaseSIMDThreeSameVectorFMLIndex<bit Q, bit U, bits<4> opc, string asm,
                                       string rhs_kind, RegisterOperand RegType,
                                       ValueType AccumType, ValueType InputType,
                                       SDPatternOperator OpNode> :
-        BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128,
+        BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128_lo,
                             VectorIndexH, asm, "", dst_kind, lhs_kind, rhs_kind,
           [(set (AccumType RegType:$dst),
                 (AccumType (OpNode (AccumType RegType:$Rd),
                                    (InputType RegType:$Rn),
-                                   (InputType (AArch64duplane16 (v8f16 V128:$Rm),
+                                   (InputType (AArch64duplane16 (v8f16 V128_lo:$Rm),
                                                 VectorIndexH:$idx)))))]> {
   // idx = H:L:M
   bits<3> idx;

diff  --git a/llvm/test/CodeGen/AArch64/fmlal-loreg.ll b/llvm/test/CodeGen/AArch64/fmlal-loreg.ll
index 39185d7aa5a571..141b1e9b882616 100644
--- a/llvm/test/CodeGen/AArch64/fmlal-loreg.ll
+++ b/llvm/test/CodeGen/AArch64/fmlal-loreg.ll
@@ -7,9 +7,12 @@
 define <4 x float> @test(ptr %lhs_panel, ptr %rhs_panel, <4 x float> %a) {
 ; CHECK-LABEL: test:
 ; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset b8, -16
 ; CHECK-NEXT:    fmov x8, d0
-; CHECK-NEXT:    ldr q16, [x0]
-; CHECK-NEXT:    ldr q17, [x1]
+; CHECK-NEXT:    ldr q8, [x0]
+; CHECK-NEXT:    ldr q16, [x1]
 ; CHECK-NEXT:    lsr x9, x8, #32
 ; CHECK-NEXT:    //APP
 ; CHECK-NEXT:    nop
@@ -17,10 +20,11 @@ define <4 x float> @test(ptr %lhs_panel, ptr %rhs_panel, <4 x float> %a) {
 ; CHECK-NEXT:    mov w8, w8
 ; CHECK-NEXT:    orr x8, x8, x9, lsl #32
 ; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    fmlal v0.4s, v17.4h, v16.h[0]
+; CHECK-NEXT:    fmlal v0.4s, v16.4h, v8.h[0]
 ; CHECK-NEXT:    mov v1.16b, v0.16b
-; CHECK-NEXT:    fmlal2 v1.4s, v17.4h, v16.h[0]
+; CHECK-NEXT:    fmlal2 v1.4s, v16.4h, v8.h[0]
 ; CHECK-NEXT:    fadd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <8 x half>, ptr %lhs_panel, align 2