[llvm-branch-commits] [llvm] 993681f - [RISCV] Add test case showing vmerge fold miscompile with tail policy

Tobias Hieta via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Wed Aug 30 08:08:36 PDT 2023


Author: Luke Lau
Date: 2023-08-30T17:00:48+02:00
New Revision: 993681f594dcad4ea279b32bcc0a2acafcd7d7c8

URL: https://github.com/llvm/llvm-project/commit/993681f594dcad4ea279b32bcc0a2acafcd7d7c8
DIFF: https://github.com/llvm/llvm-project/commit/993681f594dcad4ea279b32bcc0a2acafcd7d7c8.diff

LOG: [RISCV] Add test case showing vmerge fold miscompile with tail policy

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D158160

(cherry picked from commit 6e532f94eb0e2c9c93a3d75b4cf53bf12ab9f518)

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
index 7620ba53107203..eb1dbdfc2db56c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
@@ -1065,3 +1065,15 @@ define <vscale x 2 x i32> @vmerge_larger_vl_poison_passthru(<vscale x 2 x i32> %
   ret <vscale x 2 x i32> %b
 }
 
+; FIXME: The vadd's new policy should be tail undisturbed since the false op of
+; the vmerge moves from the the body to the tail, and we need to preserve it.
+define <vscale x 2 x i32> @vmerge_larger_vl_false_becomes_tail(<vscale x 2 x i32> %false, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
+; CHECK-LABEL: vmerge_larger_vl_false_becomes_tail:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    ret
+  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 2)
+  %b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %false, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 3)
+  ret <vscale x 2 x i32> %b
+}


        


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