[llvm-branch-commits] [llvm] 910a73d - [RISCV] Fix a UBSAN failure for passing INT64_MIN to std::abs.

[Tobias Hieta via llvm-branch-commits]

Author: Craig Topper
Date: 2023-08-21T10:05:59+02:00
New Revision: 910a73d3e97f77a053f5bb1690d8ce44ef77bbf9

URL: https://github.com/llvm/llvm-project/commit/910a73d3e97f77a053f5bb1690d8ce44ef77bbf9
DIFF: https://github.com/llvm/llvm-project/commit/910a73d3e97f77a053f5bb1690d8ce44ef77bbf9.diff

LOG: [RISCV] Fix a UBSAN failure for passing INT64_MIN to std::abs.

clang recently started checking for INT64_MIN being passed to 64-bit std::abs.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D158304

(cherry picked from commit 078eb4bd85ddaac530bf2919bb32c6daa6c3e36f)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8e248d22b57768..f030982cb815d7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3113,12 +3113,13 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
     bool Negate = false;
     int64_t SplatStepVal = StepNumerator;
     unsigned StepOpcode = ISD::MUL;
-    if (StepNumerator != 1) {
-      if (isPowerOf2_64(std::abs(StepNumerator))) {
-        Negate = StepNumerator < 0;
-        StepOpcode = ISD::SHL;
-        SplatStepVal = Log2_64(std::abs(StepNumerator));
-      }
+    // Exclude INT64_MIN to avoid passing it to std::abs. We won't optimize it
+    // anyway as the shift of 63 won't fit in uimm5.
+    if (StepNumerator != 1 && StepNumerator != INT64_MIN &&
+        isPowerOf2_64(std::abs(StepNumerator))) {
+      Negate = StepNumerator < 0;
+      StepOpcode = ISD::SHL;
+      SplatStepVal = Log2_64(std::abs(StepNumerator));
     }
 
     // Only emit VIDs with suitably-small steps/addends. We use imm5 is a