[llvm-branch-commits] [llvm] 242fe2d - [SelectionDAG] Use TypeSize variant of ComputeValueVTs to compute correct offsets for scalable aggregate types.
Tobias Hieta via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Aug 18 00:53:18 PDT 2023
Author: Paul Walker
Date: 2023-08-18T09:50:57+02:00
New Revision: 242fe2d8d86e643e70443292751a08c456862198
URL: https://github.com/llvm/llvm-project/commit/242fe2d8d86e643e70443292751a08c456862198
DIFF: https://github.com/llvm/llvm-project/commit/242fe2d8d86e643e70443292751a08c456862198.diff
LOG: [SelectionDAG] Use TypeSize variant of ComputeValueVTs to compute correct offsets for scalable aggregate types.
Differential Revision: https://reviews.llvm.org/D157872
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll
llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 5c1b19eba1c1f0..30d2024943206b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1945,6 +1945,9 @@ SDValue SelectionDAG::getVScale(const SDLoc &DL, EVT VT, APInt MulImm,
assert(MulImm.getBitWidth() == VT.getSizeInBits() &&
"APInt size does not match type size!");
+ if (MulImm == 0)
+ return getConstant(0, DL, VT);
+
if (ConstantFold) {
const MachineFunction &MF = getMachineFunction();
auto Attr = MF.getFunction().getFnAttribute(Attribute::VScaleRange);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index d3882372efcdb1..20c37eb4cb11d5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4192,7 +4192,7 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
Type *Ty = I.getType();
SmallVector<EVT, 4> ValueVTs, MemVTs;
- SmallVector<uint64_t, 4> Offsets;
+ SmallVector<TypeSize, 4> Offsets;
ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets, 0);
unsigned NumValues = ValueVTs.size();
if (NumValues == 0)
@@ -4250,9 +4250,14 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
ChainI = 0;
}
- SDValue A = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(Offsets[i]));
- SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A,
- MachinePointerInfo(SV, Offsets[i]), Alignment,
+ // TODO: MachinePointerInfo only supports a fixed length offset.
+ MachinePointerInfo PtrInfo =
+ !Offsets[i].isScalable() || Offsets[i].isZero()
+ ? MachinePointerInfo(SV, Offsets[i].getKnownMinValue())
+ : MachinePointerInfo();
+
+ SDValue A = DAG.getObjectPtrOffset(dl, Ptr, Offsets[i]);
+ SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A, PtrInfo, Alignment,
MMOFlags, AAInfo, Ranges);
Chains[ChainI] = L.getValue(1);
@@ -4354,7 +4359,7 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
}
SmallVector<EVT, 4> ValueVTs, MemVTs;
- SmallVector<uint64_t, 4> Offsets;
+ SmallVector<TypeSize, 4> Offsets;
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
SrcV->getType(), ValueVTs, &MemVTs, &Offsets, 0);
unsigned NumValues = ValueVTs.size();
@@ -4385,13 +4390,18 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
ChainI = 0;
}
- SDValue Add = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(Offsets[i]));
+ // TODO: MachinePointerInfo only supports a fixed length offset.
+ MachinePointerInfo PtrInfo =
+ !Offsets[i].isScalable() || Offsets[i].isZero()
+ ? MachinePointerInfo(PtrV, Offsets[i].getKnownMinValue())
+ : MachinePointerInfo();
+
+ SDValue Add = DAG.getObjectPtrOffset(dl, Ptr, Offsets[i]);
SDValue Val = SDValue(Src.getNode(), Src.getResNo() + i);
if (MemVTs[i] != ValueVTs[i])
Val = DAG.getPtrExtOrTrunc(Val, dl, MemVTs[i]);
SDValue St =
- DAG.getStore(Root, dl, Val, Add, MachinePointerInfo(PtrV, Offsets[i]),
- Alignment, MMOFlags, AAInfo);
+ DAG.getStore(Root, dl, Val, Add, PtrInfo, Alignment, MMOFlags, AAInfo);
Chains[ChainI] = St;
}
diff --git a/llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll b/llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll
index 0984b6b67045e4..cc0f441d0aaae4 100644
--- a/llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll
+++ b/llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll
@@ -12,16 +12,13 @@ define void @test(ptr %addr) #0 {
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: mov x8, #2 // =0x2
-; CHECK-NEXT: mov x9, #4 // =0x4
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x10, sp
-; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
-; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, x9, lsl #3]
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
-; CHECK-NEXT: st1d { z0.d }, p0, [x10, x8, lsl #3]
-; CHECK-NEXT: st1d { z1.d }, p0, [x10, x9, lsl #3]
; CHECK-NEXT: st1d { z2.d }, p0, [sp]
+; CHECK-NEXT: st1d { z1.d }, p0, [sp, #2, mul vl]
+; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll b/llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
index b220cf7315c77e..9038fa698fe3b1 100644
--- a/llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
@@ -473,7 +473,7 @@ define <4 x i32> @typesize_regression_test_v4i32(i32* %addr, i64 %idx) {
entry:
%ptr = getelementptr inbounds i32, i32* %addr, i64 %idx
%bc = bitcast i32* %ptr to <vscale x 4 x i32>*
- %ld = load <vscale x 4 x i32>, <vscale x 4 x i32>* %bc, align 16
+ %ld = load volatile <vscale x 4 x i32>, <vscale x 4 x i32>* %bc, align 16
%out = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %ld, i64 0)
ret <4 x i32> %out
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
index bf6293dbd4208a..90adbc24178633 100644
--- a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
@@ -15,15 +15,16 @@ define <vscale x 1 x double> @test(%struct.test* %addr, i64 %vl) {
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
-; CHECK-NEXT: addi a2, a0, 8
+; CHECK-NEXT: csrrs a2, vlenb, zero
+; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: vl1re64.v v8, (a3)
+; CHECK-NEXT: vl1re64.v v9, (a0)
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vs1r.v v8, (a2)
+; CHECK-NEXT: vs1r.v v9, (a0)
; CHECK-NEXT: vl1re64.v v8, (a2)
; CHECK-NEXT: vl1re64.v v9, (a0)
-; CHECK-NEXT: addi a0, sp, 24
-; CHECK-NEXT: vs1r.v v8, (a0)
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs1r.v v9, (a2)
-; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v8, v9, v8
; CHECK-NEXT: csrrs a0, vlenb, zero
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