[llvm-branch-commits] [llvm] 0af7e5e - [PowerPC][MC] Recognize tlbilx and its mnemonics

[Tobias Hieta via llvm-branch-commits]

Author: Qiu Chaofan
Date: 2023-08-03T09:01:43+02:00
New Revision: 0af7e5e54a8c7ac665773ac1ada328713e8338f5

URL: https://github.com/llvm/llvm-project/commit/0af7e5e54a8c7ac665773ac1ada328713e8338f5
DIFF: https://github.com/llvm/llvm-project/commit/0af7e5e54a8c7ac665773ac1ada328713e8338f5.diff

LOG: [PowerPC][MC] Recognize tlbilx and its mnemonics

This fixes issue 64080. tlbilx exists in ISA 2.07 Book III-E. Since
contents of Book III-E were eliminated after ISA 3.0, tlbilx does not
exist in ISA 3.0 and ISA 3.1.

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D156204

(cherry picked from commit 53648ac1d0c953ae6d008864dd2eddb437a92468)

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrFormats.td
    llvm/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/lib/Target/PowerPC/PPCScheduleP9.td
    llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 0081c0f5295a36..224c7b281ac446 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -461,6 +461,12 @@ class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
   let RST = 0;
 }
 
+class XForm_tlbilx<bits<10> xo, dag OOL, dag IOL, string asmstr,
+      InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
+  bits<5> T;
+  let RST = T;
+}
+
 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                  InstrItinClass itin>
   : I<opcode, OOL, IOL, asmstr, itin> {

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 616f4e48cfb88a..2992f78aa38ad7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4317,6 +4317,9 @@ def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB",
 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB",
                 IIC_LdStLoad>, Requires<[IsBookE]>;
 
+def TLBILX : XForm_tlbilx<18, (outs), (ins u2imm:$T, gprc:$RA, gprc:$RB),
+    "tlbilx $T, $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>;
+
 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
                            "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
 
@@ -4680,6 +4683,12 @@ def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
                 Requires<[IsPPC4xx]>;
 
+def : InstAlias<"tlbilxlpid", (TLBILX 0, R0, R0)>, Requires<[IsBookE]>;
+def : InstAlias<"tlbilxpid", (TLBILX 1, R0, R0)>, Requires<[IsBookE]>;
+def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>,
+                Requires<[IsBookE]>;
+def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>;
+
 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
 
 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",

diff  --git a/llvm/lib/Target/PowerPC/PPCScheduleP9.td b/llvm/lib/Target/PowerPC/PPCScheduleP9.td
index e9f4daa62de3cc..b763191d980e46 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -42,7 +42,7 @@ def P9Model : SchedMachineModel {
   // Power 9, or MMA, or paired vector mem ops,  or PC relative mem ops, or
   // instructions introduced after ISA 3.0.
   let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA,
-                             PairedVectorMemops,
+                             PairedVectorMemops, IsBookE,
                              PCRelativeMemops, IsISA3_1, IsISAFuture];
 }
 

diff  --git a/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s b/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
index 503001aff08547..e08434058f28a9 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
@@ -170,6 +170,26 @@
 # CHECK-LE: tlbie 4                         # encoding: [0x64,0x22,0x00,0x7c]
             tlbie %r4
 
+# CHECK-BE: tlbilx 1, 4, 5                  # encoding: [0x7c,0x24,0x28,0x24]
+# CHECK-LE: tlbilx 1, 4, 5                  # encoding: [0x24,0x28,0x24,0x7c]
+            tlbilx 1, %r4, %r5
+
+# CHECK-BE: tlbilxlpid                      # encoding: [0x7c,0x00,0x00,0x24]
+# CHECK-LE: tlbilxlpid                      # encoding: [0x24,0x00,0x00,0x7c]
+            tlbilxlpid
+
+# CHECK-BE: tlbilxpid                       # encoding: [0x7c,0x20,0x00,0x24]
+# CHECK-LE: tlbilxpid                       # encoding: [0x24,0x00,0x20,0x7c]
+            tlbilxpid
+
+# CHECK-BE: tlbilxva 4, 5                   # encoding: [0x7c,0x64,0x28,0x24]
+# CHECK-LE: tlbilxva 4, 5                   # encoding: [0x24,0x28,0x64,0x7c]
+            tlbilxva %r4, %r5
+
+# CHECK-BE: tlbilxva 0, 5                   # encoding: [0x7c,0x60,0x28,0x24]
+# CHECK-LE: tlbilxva 0, 5                   # encoding: [0x24,0x28,0x60,0x7c]
+            tlbilxva %r5
+
 # CHECK-BE: rfi                             # encoding: [0x4c,0x00,0x00,0x64]
 # CHECK-LE: rfi                             # encoding: [0x64,0x00,0x00,0x4c]
             rfi