[llvm-branch-commits] [clang] fcf0d0b - [docs] Add release notes for the LLVM 17 RVV intrinsics support

[Tobias Hieta via llvm-branch-commits]

Author: eopXD
Date: 2023-08-01T10:26:22+02:00
New Revision: fcf0d0ba9c051ea7042490147148f67f0ea9a1b3

URL: https://github.com/llvm/llvm-project/commit/fcf0d0ba9c051ea7042490147148f67f0ea9a1b3
DIFF: https://github.com/llvm/llvm-project/commit/fcf0d0ba9c051ea7042490147148f67f0ea9a1b3.diff

LOG: [docs] Add release notes for the LLVM 17 RVV intrinsics support

Added: 
    

Modified: 
    clang/docs/ReleaseNotes.rst

Removed: 
    


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diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index d4a08062352fa4..0511284e856c3d 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -927,6 +927,18 @@ RISC-V Support
 - The rules for ordering of extensions in ``-march`` strings were relaxed. A
   canonical ordering is no longer enforced on ``z*``, ``s*``, and ``x*``
   prefixed extensions.
+- Support the RVV intrinsics v0.12. Please checkout `the RVV C intrinsics
+  specification
+  <https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v0.12.0>`_.
+  It is expected there won't be any incompatibility from this v0.12 to the
+  specifications planned for v1.0.
+
+  * Added vector intrinsics that models control to the rounding mode
+    (``frm`` and ``vxrm``) for the floating-point instruction intrinsics and the 
+    fixed-point instruction intrinsics.
+  * Added intrinsics for reinterpret cast between vector boolean and vector
+    integer ``m1`` value
+  * Removed the ``vread_csr`` and ``vwrite_csr`` intrinsics
 
 CUDA/HIP Language Changes
 ^^^^^^^^^^^^^^^^^^^^^^^^^