[llvm-branch-commits] [llvm] 02b2c02 - [PowerPC] Precommit testcases for regpressure compute fix

Jinsong Ji via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Tue Dec 8 19:42:08 PST 2020


Author: Jinsong Ji
Date: 2020-12-09T03:37:00Z
New Revision: 02b2c024193b1985d85855a7f85b98aef9ebbcdb

URL: https://github.com/llvm/llvm-project/commit/02b2c024193b1985d85855a7f85b98aef9ebbcdb
DIFF: https://github.com/llvm/llvm-project/commit/02b2c024193b1985d85855a7f85b98aef9ebbcdb.diff

LOG: [PowerPC] Precommit testcases for regpressure compute fix

Added: 
    llvm/test/CodeGen/PowerPC/compute-regpressure.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/compute-regpressure.ll b/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
new file mode 100644
index 000000000000..7a15e4677267
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
@@ -0,0 +1,30 @@
+; REQUIRES: asserts
+; RUN: llc -debug-only=regalloc < %s 2>&1 |FileCheck %s --check-prefix=DEBUG
+
+; DEBUG-COUNT-3:         AllocationOrder(VRSAVERC) = [ ]
+
+target triple = "powerpc64le-unknown-linux-gnu"
+
+define hidden fastcc void @test() {
+freescalar:
+  %0 = load i32, i32* undef, align 4
+  br label %if.end420
+
+if.end420:                                        ; preds = %freescalar
+  br label %free_rv
+
+free_rv:                                          ; preds = %if.end420
+  %and427 = and i32 %0, -2147481600
+  %cmp428 = icmp eq i32 %and427, -2147481600
+  br i1 %cmp428, label %if.then430, label %free_body
+
+if.then430:                                       ; preds = %free_rv
+  call fastcc void undef()
+  br label %free_body
+
+free_body:                                        ; preds = %if.then430, %free_rv
+  %or502 = or i32 undef, 255
+  store i32 %or502, i32* undef, align 4
+  ret void
+}
+


        


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