[llvm-branch-commits] [llvm] 1348294 - baseline
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Nov 8 01:30:28 PST 2019
Author: joanlluch
Date: 2019-10-17T12:27:20+02:00
New Revision: 134829441250e27a8c41b01cdb562f27842947bc
URL: https://github.com/llvm/llvm-project/commit/134829441250e27a8c41b01cdb562f27842947bc
DIFF: https://github.com/llvm/llvm-project/commit/134829441250e27a8c41b01cdb562f27842947bc.diff
LOG: baseline
Added:
llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll b/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
new file mode 100644
index 000000000000..19acb5f19739
--- /dev/null
+++ b/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
@@ -0,0 +1,189 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"
+target triple = "msp430"
+
+define dso_local i16 @test000a(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test000a:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: and #32, r12
+; CHECK-NEXT: clrc
+; CHECK-NEXT: rrc r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: ret
+entry:
+ %and = and i16 %a, 32
+ %cmp = icmp ne i16 %and, 0
+ %conv = zext i1 %cmp to i16
+ ret i16 %conv
+}
+
+define dso_local i16 @test000b(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test000b:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: and #32, r12
+; CHECK-NEXT: clrc
+; CHECK-NEXT: rrc r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: ret
+entry:
+ %and = and i16 %a, 32
+ %cmp = icmp eq i16 %and, 32
+ %conv = zext i1 %cmp to i16
+ ret i16 %conv
+}
+
+define dso_local i16 @test000(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test000:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov r12, r13
+; CHECK-NEXT: clr r12
+; CHECK-NEXT: bit #2048, r13
+; CHECK-NEXT: jeq .LBB2_2
+; CHECK-NEXT: ; %bb.1: ; %entry
+; CHECK-NEXT: mov #3, r12
+; CHECK-NEXT: .LBB2_2: ; %entry
+; CHECK-NEXT: ret
+entry:
+ %and = and i16 %a, 2048
+ %cmp = icmp eq i16 %and, 0
+ %cond = select i1 %cmp, i16 0, i16 3
+ ret i16 %cond
+}
+
+define dso_local i16 @test00(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test00:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: inv r12
+; CHECK-NEXT: swpb r12
+; CHECK-NEXT: mov.b r12, r12
+; CHECK-NEXT: clrc
+; CHECK-NEXT: rrc r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: ret
+entry:
+ %cmp = icmp sgt i16 %a, -1
+ %cond = select i1 %cmp, i16 1, i16 0
+ ret i16 %cond
+}
+
+define dso_local i16 @test0(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test0:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: swpb r12
+; CHECK-NEXT: sxt r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: ret
+entry:
+ %cmp = icmp slt i16 %a, 0
+ %cond = select i1 %cmp, i16 -1, i16 0
+ ret i16 %cond
+}
+
+define dso_local i16 @test1(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test1:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: swpb r12
+; CHECK-NEXT: mov.b r12, r12
+; CHECK-NEXT: clrc
+; CHECK-NEXT: rrc r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: ret
+entry:
+ %cmp = icmp slt i16 %a, 0
+ %cond = select i1 %cmp, i16 1, i16 0
+ ret i16 %cond
+}
+
+define dso_local i16 @test2(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test2:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: swpb r12
+; CHECK-NEXT: mov.b r12, r12
+; CHECK-NEXT: clrc
+; CHECK-NEXT: rrc r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: and #2, r12
+; CHECK-NEXT: ret
+entry:
+ %cmp = icmp slt i16 %a, 0
+ %cond = select i1 %cmp, i16 2, i16 0
+ ret i16 %cond
+}
+
+define dso_local i16 @test3(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test3:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: swpb r12
+; CHECK-NEXT: sxt r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: rra r12
+; CHECK-NEXT: and #3, r12
+; CHECK-NEXT: ret
+entry:
+ %cmp = icmp slt i16 %a, 0
+ %cond = select i1 %cmp, i16 3, i16 0
+ ret i16 %cond
+}
+
+define dso_local i16 @test4(i16 %a, i16 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: test4:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov r12, r14
+; CHECK-NEXT: mov #1, r12
+; CHECK-NEXT: cmp r14, r13
+; CHECK-NEXT: jl .LBB8_2
+; CHECK-NEXT: ; %bb.1: ; %entry
+; CHECK-NEXT: clr r12
+; CHECK-NEXT: .LBB8_2: ; %entry
+; CHECK-NEXT: add r12, r12
+; CHECK-NEXT: add r12, r12
+; CHECK-NEXT: add r12, r12
+; CHECK-NEXT: add r12, r12
+; CHECK-NEXT: add r12, r12
+; CHECK-NEXT: ret
+entry:
+ %cmp = icmp sgt i16 %a, %b
+ %cond = select i1 %cmp, i16 32, i16 0
+ ret i16 %cond
+}
+
+
+attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 2}
+!1 = !{!"clang version 9.0.0 (https://github.com/llvm/llvm-project.git ad1d7b8d698478b36a32afd45bf0c57b2a08c6bd)"}
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