[llvm-branch-commits] [cfe-branch] r369649 - Merging r369093:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Thu Aug 22 06:42:47 2019
New Revision: 369649

URL: http://llvm.org/viewvc/llvm-project?rev=369649&view=rev
Log:
Merging r369093:
------------------------------------------------------------------------
r369093 | lewis-revill | 2019-08-16 12:23:56 +0200 (Fri, 16 Aug 2019) | 11 lines

[RISCV] Add inline asm constraint A for RISC-V

This allows the constraint A to be used in inline asm for RISC-V, which
allows an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

Differential Revision: https://reviews.llvm.org/D54295


------------------------------------------------------------------------

Modified:
    cfe/branches/release_90/   (props changed)
    cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp
    cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c

Propchange: cfe/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Aug 22 06:42:47 2019
@@ -1,4 +1,4 @@
 /cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:366429,366448,366457,366474,366480,366483,366511,366670,366694,366699,366878,367008,367039,367055,367103,367134,367301,367305,367323,367387,367403,367520,367530,367661,367675,367802,367823,367906,368104,368202,368552,368561,368874,368940,369043,369251
+/cfe/trunk:366429,366448,366457,366474,366480,366483,366511,366670,366694,366699,366878,367008,367039,367055,367103,367134,367301,367305,367323,367387,367403,367520,367530,367661,367675,367802,367823,367906,368104,368202,368552,368561,368874,368940,369043,369093,369251
 /cfe/trunk/test:170344
 /cfe/trunk/test/SemaTemplate:126920

Modified: cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp?rev=369649&r1=369648&r2=369649&view=diff
==============================================================================
--- cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp (original)
+++ cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp Thu Aug 22 06:42:47 2019
@@ -60,6 +60,10 @@ bool RISCVTargetInfo::validateAsmConstra
     // A floating-point register.
     Info.setAllowsRegister();
     return true;
+  case 'A':
+    // An address that is held in a general-purpose register.
+    Info.setAllowsMemory();
+    return true;
   }
 }
 

Modified: cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c?rev=369649&r1=369648&r2=369649&view=diff
==============================================================================
--- cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c (original)
+++ cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c Thu Aug 22 06:42:47 2019
@@ -38,3 +38,9 @@ void test_f() {
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}