[llvm-branch-commits] [llvm-branch] r235864 - Merging r227430:
Daniel Sanders
daniel.sanders at imgtec.com
Mon Apr 27 04:59:50 PDT 2015
Author: dsanders
Date: Mon Apr 27 06:59:49 2015
New Revision: 235864
URL: http://llvm.org/viewvc/llvm-project?rev=235864&view=rev
Log:
Merging r227430:
------------------------------------------------------------------------
r227430 | vmedic | 2015-01-29 11:33:41 +0000 (Thu, 29 Jan 2015) | 1 line
[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
------------------------------------------------------------------------
Modified:
llvm/branches/release_36/ (props changed)
llvm/branches/release_36/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/branches/release_36/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
Propchange: llvm/branches/release_36/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Apr 27 06:59:49 2015
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,226023,226029,226044,226046,226048,226058,226075,226151,226164-226166,226170-226171,226182,226407-226409,226473,226588,226616,226652,226664,226708,226711,226755,226791,226808-226809,226905,227005,227084-227085,227087,227089,227250,227260-227261,227269,227290,227294,227299,227319,227339,227491,227584,227603,227628,227670,227809,227815,227903,227934,227972,227983,228049,228129,228168,228331,228411,228444,228490,228500,228507,228518,228525,228565,228656,228760-228761,228793,228842,228899,228957,228969,228979,229029,229343,229351-229352,229421,229495,229529,229731,229911,230058,231219,231227,231563,231601,232046,232085,232189
+/llvm/trunk:155241,226023,226029,226044,226046,226048,226058,226075,226151,226164-226166,226170-226171,226182,226407-226409,226473,226588,226616,226652,226664,226708,226711,226755,226791,226808-226809,226905,227005,227084-227085,227087,227089,227250,227260-227261,227269,227290,227294,227299,227319,227339,227430,227491,227584,227603,227628,227670,227809,227815,227903,227934,227972,227983,228049,228129,228168,228331,228411,228444,228490,228500,228507,228518,228525,228565,228656,228760-228761,228793,228842,228899,228957,228969,228979,229029,229343,229351-229352,229421,229495,229529,229731,229911,230058,231219,231227,231563,231601,232046,232085,232189
Modified: llvm/branches/release_36/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=235864&r1=235863&r2=235864&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/branches/release_36/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Mon Apr 27 06:59:49 2015
@@ -259,6 +259,11 @@ static DecodeStatus DecodeCacheOp(MCInst
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -1115,6 +1120,23 @@ static DecodeStatus DecodeCacheOpMM(MCIn
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+ Inst.addOperand(MCOperand::CreateReg(Base));
+ Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::CreateImm(Hint));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ int Offset = fieldFromInstruction(Insn, 7, 9);
+ unsigned Hint = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
Inst.addOperand(MCOperand::CreateImm(Hint));
Modified: llvm/branches/release_36/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/Mips/Mips32r6InstrInfo.td?rev=235864&r1=235863&r2=235864&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/branches/release_36/lib/Target/Mips/Mips32r6InstrInfo.td Mon Apr 27 06:59:49 2015
@@ -549,6 +549,7 @@ class CACHE_HINT_DESC<string instr_asm,
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
list<dag> Pattern = [];
+ string DecoderMethod = "DecodeCacheOpR6";
}
class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
Modified: llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt?rev=235864&r1=235863&r2=235864&view=diff
==============================================================================
--- llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt (original)
+++ llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt Mon Apr 27 06:59:49 2015
@@ -144,3 +144,5 @@
0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
+0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
+0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5
Modified: llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt?rev=235864&r1=235863&r2=235864&view=diff
==============================================================================
--- llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt (original)
+++ llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt Mon Apr 27 06:59:49 2015
@@ -144,4 +144,5 @@
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
-
+0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
+0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
Modified: llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt?rev=235864&r1=235863&r2=235864&view=diff
==============================================================================
--- llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt (original)
+++ llvm/branches/release_36/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt Mon Apr 27 06:59:49 2015
@@ -13,5 +13,3 @@
0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256
0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
-0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
-0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
Modified: llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt?rev=235864&r1=235863&r2=235864&view=diff
==============================================================================
--- llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt (original)
+++ llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt Mon Apr 27 06:59:49 2015
@@ -162,4 +162,5 @@
0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
-
+0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
+0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)
Modified: llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt?rev=235864&r1=235863&r2=235864&view=diff
==============================================================================
--- llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt (original)
+++ llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt Mon Apr 27 06:59:49 2015
@@ -162,4 +162,5 @@
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
-
+0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
+0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
Modified: llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt?rev=235864&r1=235863&r2=235864&view=diff
==============================================================================
--- llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt (original)
+++ llvm/branches/release_36/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt Mon Apr 27 06:59:49 2015
@@ -13,8 +13,6 @@
0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256
0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
-0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
-0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025
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