[cfe-dev] RFC: TileGX, a new backend for Tilera's many core processor
jiwang at tilera.com
Thu Feb 28 16:09:20 PST 2013
On behalf of Tilera Corporation, I'd like to contribute llvm ports to
architecture and wish this could be submitted to main llvm tree.
TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address space,
and 64-bit instructions. TILE-Gx has load-store architecture ISAs.
More information on the architectures is available at
the attached patches contains the following main features for tilegx
1. general function.
3. Instructoin Bundling for VLIW.
4. Basic support for Asm Parser.
5. MC Layer (aware of VLIW), MCJIT support.
I've run the regression test and standalone test-suite natively on
TILE-Gx silicon. The
test results are:
Expected Passes : 13218
Expected Failures : 78
Unsupported Tests : 68
Unexpected Failures: 44
Expected Passes : 949
Unexpected Failures: 17
the llvm patch is against:
Author: Evgeniy Stepanov <eugeni.stepanov at gmail.com>
Date: Thu Feb 28 11:25:14 2013 +0000
[msan] Implement sanitize_memory attribute.
the clang patch is against:
Author: Daniel Jasper <djasper at google.com>
Date: Thu Feb 28 11:05:57 2013 +0000
Improve formatting of #defines.
the test-suite patch is against:
Author: Duncan Sands <baldrick at free.fr>
Date: Sun Feb 17 15:21:11 2013 +0000
Use LLVMCC_EMITIR_FLAG rather than -emit-llvm
please review, looking forward to your feedback.
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