[clang] [llvm] [arm] Support reserving r4 and r5 alongside r9 (PR #89849)

[Peter Smith via cfe-commits]

https://github.com/smithp35 commented:

There was a previous attempt at doing something similar with more global registers r6-r11 in https://reviews.llvm.org/D68862 based on http://lists.llvm.org/pipermail/llvm-dev/2018-December/128706.html

This got reverted, and unfortunately didn't get picked back up. 

One of the comments in the description of the patch is:
```
Additionally this patch now only supports r6-r11. r4 and r5 are excluded from this patch as r4 is used as hard-coded scratch register in various parts of the ARM backend. r4 also appears to be used as an input register for a Windows asm routine (__chkstk). Similarly, the ABI of the segmented stack prologue for Android and Linux seems to use r4 and r5 as input registers. A separate patch could follow to add the support for r4 and/or r5, such that the whole range of allocatable registers (r4-r11) is available.
```

My suggestions:
* Describe why R4 and R5 specifically and not R6 - R11?
* If R4 and R5 are required then show that the hard-coded use in the backend is no longer there. If R4 and R5 are not required I suggest picking up the changes in https://reviews.llvm.org/D68862
* Add tests, especially if registers that have other uses in procedure call standards, or frame chains are used.
* Given that the original was reverted due to interactions with r6, explain what further tests that you've made such as compiling large bodies of code or fuzz tested against programs. 

https://github.com/llvm/llvm-project/pull/89849