[clang] [llvm] [AMDGPU][WIP] Add support for i64/f64 readlane, writelane and readfirstlane operations. (PR #89217)

[Matt Arsenault via cfe-commits]

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@@ -4822,6 +4822,111 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
   return RetBB;
 }
 
+static MachineBasicBlock *lowerPseudoLaneOp(MachineInstr &MI,
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arsenm wrote:

No, that's a generic pass. I would directly handle this in the legalizer, in SIISelLowering and AMDGPULegalizer 

https://github.com/llvm/llvm-project/pull/89217