[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

> However, manually adding the required target feature seems a little mistakable, like the one below. I guess we can not get the required feature in the LLVM instruction TDs(if the builtin is mapped to a IR intrinsic and the intrinsic is selected inside the instruction TD) because this is done in CLANG?

Yes, this is how clang builtin definitions work. They are independent from LLVM definitions in tablegen files.

> Really need to way to make sure that the instruction are marked with the accurate target feature, if not possible to do this inside the compiler, an offline script maybe? Checking the instruction one by one is a little time-consuming.

I actually don't think we need extra script to maintain this. They're rather static (not willing to change after written), independent (one changed won't affect another) and human-readable.



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Comment at: clang/include/clang/Basic/BuiltinsPPC.def:491
+TARGET_BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us", "", "altivec")
+TARGET_BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui", "", "altivec")
 
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shchenz wrote:
> These builtins `vabsdub`, `vabsduh`, `vabsduw`  should require ISA3.0 which is not altivec or vsx. Do we have a reasonable feature for Power9 instructions, `power9-vector` maybe?
Thanks. I'll update then. `power9-vector` is good option. But I'm curious what's the different pratical usages from `power9-vector` and `isa-v30-instructions`. Maybe cc @nemanjai 


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  https://reviews.llvm.org/D143467/new/

https://reviews.llvm.org/D143467