[PATCH] D124749: [clang-format] Handle Verilog preprocessor directives

[sstwcw via Phabricator via cfe-commits]

sstwcw added inline comments.


================
Comment at: clang/lib/Format/FormatTokenLexer.cpp:1105
+  static const llvm::Regex VerilogToken(
+      "^(\'|``?|\\\\(\\\\(\r?\n|\r)|[^[:space:]])*)");
+
----------------
HazardyKnusperkeks wrote:
> Consider a raw string, for a better reading.
You mean like this?

    static const llvm::Regex VerilogToken(R"re(^('|``?|\\(\\)re"
                                          "(\r?\n|\r)|[^[:space:]])*)");



================
Comment at: clang/lib/Format/FormatTokenLexer.cpp:1129
 void FormatTokenLexer::readRawToken(FormatToken &Tok) {
-  Lex->LexFromRawLexer(Tok.Tok);
+  if (!(Style.isVerilog() && readRawTokenVerilogSpecific(Tok.Tok)))
+    Lex->LexFromRawLexer(Tok.Tok);
----------------
HazardyKnusperkeks wrote:
> Otherwise I don't see why you change that.
The function is only supposed to be used for Verilog, so `&&` is correct. If you mean why this part is different from D121758, I changed the name from `readRawTokenLanguageSpecific` to `readRawTokenVerilogSpecific` as suggested by a reviewer. Then I moved the check for language out of that function like what `tryParseJSRegexLiteral` does.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124749/new/

https://reviews.llvm.org/D124749