[PATCH] D123450: [clang-format] Parse Verilog if statements

[sstwcw via Phabricator via cfe-commits]

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This patch mainly handles treating `begin` as block openers.

While and for statements will be handled in another patch.

We added an alias option in FormatToken to treat a token as another
token.  This way when some language uses an alternative symbol like
backtick for hash we can continue using tok::hash in the code.  For
keywords like `begin`, left braces aren't block openers in if
expressions while they are in structs and enums.  That means we can't
simply treat `begin` and the left brace the same way.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123450

Files:
  clang/docs/ClangFormat.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/QualifierAlignmentFixer.cpp
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/UnwrappedLineFormatter.cpp
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/tools/clang-format/ClangFormat.cpp
  clang/unittests/Format/CMakeLists.txt
  clang/unittests/Format/FormatTestUtils.h
  clang/unittests/Format/FormatTestVerilog.cpp

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