[PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:624
+                              (mask_type true_mask),
+                              VLOpFrag, (XLenVT undef))),
+            (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
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I don't like using Undef for a field that should be a constant. Can we use 0?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120449/new/

https://reviews.llvm.org/D120449