[PATCH] D105626: [RISCV][Clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins

[Jianjian Guan via Phabricator via cfe-commits]

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Add extension macro __riscv_zvlsseg to enable Zvlsseg builtins only with target feature Zvlsseg.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105626

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===================================================================
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -141,6 +141,7 @@
   D = 1 << 2,
   Zfh = 1 << 3,
   Zvamo = 1 << 4,
+  Zvlsseg = 1 << 5,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -784,6 +785,8 @@
   }
   if (RequiredExtension == "Zvamo")
     RISCVExtensions |= RISCVExtension::Zvamo;
+  if (RequiredExtension == "Zvlsseg")
+    RISCVExtensions |= RISCVExtension::Zvlsseg;
 
   // Init OutputType and InputTypes
   OutputType = OutInTypes[0];
@@ -1237,6 +1240,8 @@
     OS << LS << "defined(__riscv_zfh)";
   if (Extents & RISCVExtension::Zvamo)
     OS << LS << "defined(__riscv_zvamo)";
+  if (Extents & RISCVExtension::Zvlsseg)
+    OS << LS << "defined(__riscv_zvlsseg)";
   OS << "\n";
   return true;
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 


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