[PATCH] D101606: [ARM][MVE] vcreateq lane ordering for big endian

[Mark Murray via Phabricator via cfe-commits]

MarkMurrayARM added inline comments.


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Comment at: clang/test/CodeGen/arm-mve-intrinsics/admin.c:66
 // CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
 // CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 //
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dmgreen wrote:
> MarkMurrayARM wrote:
> > Surely there is a problem here also?
> I don't see why these would be a problem. Can you elaborate?
I'm wondering if they need to be swapped in the BE case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101606/new/

https://reviews.llvm.org/D101606