[clang] 002f5ab - [clang][aarch64] Fix ILP32 ABI for arm_sve_vector_bits
Cullen Rhodes via cfe-commits
cfe-commits at lists.llvm.org
Fri Sep 11 02:47:46 PDT 2020
Author: Cullen Rhodes
Date: 2020-09-11T09:46:35Z
New Revision: 002f5ab3b171c7d9c9ea192b04a5303be78f6e52
URL: https://github.com/llvm/llvm-project/commit/002f5ab3b171c7d9c9ea192b04a5303be78f6e52
DIFF: https://github.com/llvm/llvm-project/commit/002f5ab3b171c7d9c9ea192b04a5303be78f6e52.diff
LOG: [clang][aarch64] Fix ILP32 ABI for arm_sve_vector_bits
The element types of scalable vectors are defined in terms of stdint
types in the ACLE. This patch fixes the mapping to builtin types for the
ILP32 ABI when creating VLS types with the arm_sve_vector_bits, where
the mapping is as follows:
int32_t -> LongTy
int64_t -> LongLongTy
uint32_t -> UnsignedLongTy
uint64_t -> UnsignedLongLongTy
This is implemented by leveraging getBuiltinVectorTypeInfo which is
target agnostic since it calls ASTContext::getIntTypeForBitwidth for
integer types. The element type for svfloat16_t is changed from
Float16Ty to HalfTy when creating VLS types since this is what is used
elsewhere.
For more information, see:
https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#types-varying-by-data-model
https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-support-for-scalable-vectors
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D87358
Added:
Modified:
clang/lib/AST/ItaniumMangle.cpp
clang/lib/AST/Type.cpp
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/attr-arm-sve-vector-bits-types.c
Removed:
################################################################################
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index d8ccbdaba9c60..877050c160955 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -3388,7 +3388,7 @@ void CXXNameMangler::mangleAArch64FixedSveVectorType(const VectorType *T) {
case BuiltinType::ULong:
TypeName = "__SVUint64_t";
break;
- case BuiltinType::Float16:
+ case BuiltinType::Half:
TypeName = "__SVFloat16_t";
break;
case BuiltinType::Float:
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index 801f89a8f1874..ff73a7340091e 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -2317,38 +2317,13 @@ QualType Type::getSveEltType(const ASTContext &Ctx) const {
assert(isVLSTBuiltinType() && "unsupported type!");
const BuiltinType *BTy = getAs<BuiltinType>();
- switch (BTy->getKind()) {
- default:
- llvm_unreachable("Unknown builtin SVE type!");
- case BuiltinType::SveInt8:
- return Ctx.SignedCharTy;
- case BuiltinType::SveUint8:
- case BuiltinType::SveBool:
+ if (BTy->getKind() == BuiltinType::SveBool)
// Represent predicates as i8 rather than i1 to avoid any layout issues.
// The type is bitcasted to a scalable predicate type when casting between
// scalable and fixed-length vectors.
return Ctx.UnsignedCharTy;
- case BuiltinType::SveInt16:
- return Ctx.ShortTy;
- case BuiltinType::SveUint16:
- return Ctx.UnsignedShortTy;
- case BuiltinType::SveInt32:
- return Ctx.IntTy;
- case BuiltinType::SveUint32:
- return Ctx.UnsignedIntTy;
- case BuiltinType::SveInt64:
- return Ctx.LongTy;
- case BuiltinType::SveUint64:
- return Ctx.UnsignedLongTy;
- case BuiltinType::SveFloat16:
- return Ctx.Float16Ty;
- case BuiltinType::SveBFloat16:
- return Ctx.BFloat16Ty;
- case BuiltinType::SveFloat32:
- return Ctx.FloatTy;
- case BuiltinType::SveFloat64:
- return Ctx.DoubleTy;
- }
+ else
+ return Ctx.getBuiltinVectorTypeInfo(BTy).ElementType;
}
bool QualType::isPODType(const ASTContext &Context) const {
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index e1ab61f10585d..5ebf432a4cd36 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -5627,7 +5627,7 @@ ABIArgInfo AArch64ABIInfo::coerceIllegalVector(QualType Ty) const {
ResType = llvm::ScalableVectorType::get(
llvm::Type::getInt64Ty(getVMContext()), 2);
break;
- case BuiltinType::Float16:
+ case BuiltinType::Half:
ResType = llvm::ScalableVectorType::get(
llvm::Type::getHalfTy(getVMContext()), 8);
break;
diff --git a/clang/test/CodeGen/attr-arm-sve-vector-bits-types.c b/clang/test/CodeGen/attr-arm-sve-vector-bits-types.c
index a1cfc514081ea..27366dea3d34d 100644
--- a/clang/test/CodeGen/attr-arm-sve-vector-bits-types.c
+++ b/clang/test/CodeGen/attr-arm-sve-vector-bits-types.c
@@ -4,6 +4,7 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-512
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=1024 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-1024
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=2048 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-2048
+// RUN: %clang_cc1 -triple aarch64_32-unknown-darwin -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ILP32
#include <arm_sve.h>
@@ -579,3 +580,11 @@ void f() {
// CHECK-2048-NEXT: %local_arr_f64 = alloca [3 x <32 x double>], align 16
// CHECK-2048-NEXT: %local_arr_bf16 = alloca [3 x <128 x bfloat>], align 16
// CHECK-2048-NEXT: %local_arr_bool = alloca [3 x <32 x i8>], align 2
+
+//===----------------------------------------------------------------------===//
+// ILP32 ABI
+//===----------------------------------------------------------------------===//
+// CHECK-ILP32: @global_i32 = global <16 x i32> zeroinitializer, align 16
+// CHECK-ILP32: @global_i64 = global <8 x i64> zeroinitializer, align 16
+// CHECK-ILP32: @global_u32 = global <16 x i32> zeroinitializer, align 16
+// CHECK-ILP32: @global_u64 = global <8 x i64> zeroinitializer, align 16
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