[PATCH] D84414: [RISCV] Support Shadow Call Stack

[Sam Elliott via Phabricator via cfe-commits]

lenary added a comment.

In D84414#2186257 <https://reviews.llvm.org/D84414#2186257>, @jrtc27 wrote:

> There is a possibly-compelling argument against using x18: RV32E only gives x0-x15, so would not be able to support the current implementation.

We discussed this on the RISC-V LLVM Sync-up (both this time and on 6 August 2020 IIRC). The consensus view is: if you're on an rv32e implementation, you're potentially too constrained to use a shadow call stack anyway. Even then, LLVM doesn't implement the rest of rv32e yet (though there are plans to do so at some point, which means we can revisit this change).

Our feeling is that if users have a distinct need to use a different register at the moment, they can use a downstream change to LLVM. The fact that we use `RISCVABI::getSCSPReg()` should make this fairly easy.

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If the register choice is the only concern about this work, then I think we can probably land it as-is and fixup the register choice if we see major drawbacks later. Yes, it's an ABI issue, but on the other hand the shadow call stack is not a standard ABI anyway.


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