[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

Mon Aug 10 09:34:25 PDT 2020

paulwalker-arm added a comment.

In D71767#2207158 <https://reviews.llvm.org/D71767#2207158>, @cameron.mcinally wrote:

> In D71767#2206947 <https://reviews.llvm.org/D71767#2206947>, @paulwalker-arm wrote:
>
>> @cameron.mcinally this is the patch I mentioned the other day, which contains the nodes where once I've written suitable tests I'll push separate patches for.
>
> Thanks, Paul. You mentioned that you would be focusing on another project for a few weeks. Would it help if I attempted to cherry-pick some of this Diff into individual patches (with new tests) for you? Or would I be stepping on your toes too much?

That would be great, thanks.  I already have patches up for the extends and am currently focusing on setcc, sub and the shifts, which leaves min/max and divides.  That said, one area I've not looked at yet are the VECREDUCE_ nodes.  I don't anticipate them to be that problematic but having proof of this would be nice.  Let me know what you decide.

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https://reviews.llvm.org/D71767