[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

[Albion Fung via Phabricator via cfe-commits]

Conanap created this revision.
Conanap added reviewers: power-llvm-team, PowerPC, nemanjai, saghir, hfinkel.
Conanap added projects: LLVM, clang, PowerPC.

Implemented following functions for Load VSX Vector Sign extend nad zero extend instructions:

  vector signed __int128 vec_xl_sext (signed long long, signed char *);
  vector signed __int128 vec_xl_sext (signed long long, signed short *);
  vector signed __int128 vec_xl_sext (signed long long, signed int *);
  vector signed __int128 vec_xl_sext (signed long long, signed long long *);
  
  vector unsigned __int128 vec_xl_zext (signed long long, unsigned char *);
  vector unsigned __int128 vec_xl_zext (signed long long, unsigned short *);
  vector unsigned __int128 vec_xl_zext (signed long long, unsigned int *);
  vector unsigned __int128 vec_xl_zext (signed long long, unsigned long long *);


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82502

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

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