[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Evandro Menezes via Phabricator via cfe-commits]

evandro added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56
+def NoConstraint : RISCVVConstraint<0>;
+def WidenV       : RISCVVConstraint<1>;
+def WidenW       : RISCVVConstraint<2>;
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Methinks that these constraints `WidenV`, `WidenW`, `WidenCvt`, should be split up by their components.  IOW, into `Widen`, `Wide` (input), `Cvt`.  This way, it's easier to test for specific constraints.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:61
+def Narrow       : RISCVVConstraint<5>;
+def NarrowCvt    : RISCVVConstraint<6>;
+def Iota         : RISCVVConstraint<7>;
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Likewise, this constraint could then be removed, but `Narrow && Cvt` would achieve the same meaning.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D69987/new/

https://reviews.llvm.org/D69987