[PATCH] D80804: [AMDGPU] Expose llvm atomic inc/dec instructions as clang builtins for AMDGPU target

[Sameer Sahasrabuddhe via Phabricator via cfe-commits]

sameerds added inline comments.


================
Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14529-14530
+
+      // llvm.amdgcn.atomic.inc and llvm.amdgcn.atomic.dec expects ordering and
+      // scope as unsigned values
+      Value *MemOrder = Builder.getInt32(static_cast<int>(AO));
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arsenm wrote:
> We should fix this (or move these into atomicrmw)
I am not sure why these intrinsics exist as separate from atomicrmw. But while they do, taking a numerical scope is not a problem since they are target-specific. The LLVM instructions take scope as an opaque string just to keep target-specific bits out of the IR.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80804/new/

https://reviews.llvm.org/D80804