[clang] ac894a5 - [SveEmitter] Add builtins for FFR manipulation

[Sander de Smalen via cfe-commits]

Author: Sander de Smalen
Date: 2020-05-07T12:28:18+01:00
New Revision: ac894a5181ef622139a2c09b66a006e8fd450849

URL: https://github.com/llvm/llvm-project/commit/ac894a5181ef622139a2c09b66a006e8fd450849
DIFF: https://github.com/llvm/llvm-project/commit/ac894a5181ef622139a2c09b66a006e8fd450849.diff

LOG: [SveEmitter] Add builtins for FFR manipulation

This patch adds builtins for:
- svrdffr, svrdffr_z
- svsetffr
- svwrffr

Added: 
    clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c
    clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_setffr.c
    clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_wrffr.c

Modified: 
    clang/include/clang/Basic/arm_sve.td

Removed: 
    


################################################################################
diff  --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
index 4c73c98bcb52..3ae2e9e60a61 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1137,6 +1137,14 @@ def SVPTEST_ANY   : SInst<"svptest_any",   "sPP", "Pc", MergeNone, "aarch64_sve_
 def SVPTEST_FIRST : SInst<"svptest_first", "sPP", "Pc", MergeNone, "aarch64_sve_ptest_first">;
 def SVPTEST_LAST  : SInst<"svptest_last",  "sPP", "Pc", MergeNone, "aarch64_sve_ptest_last">;
 
+////////////////////////////////////////////////////////////////////////////////
+// FFR manipulation
+
+def SVRDFFR   : SInst<"svrdffr",   "P",  "Pc", MergeNone, "", [IsOverloadNone]>;
+def SVRDFFR_Z : SInst<"svrdffr_z", "PP", "Pc", MergeNone, "", [IsOverloadNone]>;
+def SVSETFFR  : SInst<"svsetffr",  "v",  "",   MergeNone, "", [IsOverloadNone]>;
+def SVWRFFR   : SInst<"svwrffr",   "vP", "Pc", MergeNone, "", [IsOverloadNone]>;
+
 ////////////////////////////////////////////////////////////////////////////////
 // Counting elements
 

diff  --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c
new file mode 100644
index 000000000000..44d2c166af10
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include <arm_sve.h>
+
+svbool_t test_svrdffr()
+{
+  // CHECK-LABEL: test_svrdffr
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr()
+  // CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
+  return svrdffr();
+}
+
+svbool_t test_svrdffr_z(svbool_t pg)
+{
+  // CHECK-LABEL: test_svrdffr_z
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg)
+  // CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
+  return svrdffr_z(pg);
+}

diff  --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_setffr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_setffr.c
new file mode 100644
index 000000000000..df9a3c647aa0
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_setffr.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include <arm_sve.h>
+
+void test_svsetffr()
+{
+  // CHECK-LABEL: test_svsetffr
+  // CHECK: call void @llvm.aarch64.sve.setffr()
+  // CHECK: ret void
+  svsetffr();
+}

diff  --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_wrffr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_wrffr.c
new file mode 100644
index 000000000000..84b3004e307c
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_wrffr.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include <arm_sve.h>
+
+void test_svwrffr(svbool_t op)
+{
+  // CHECK-LABEL: test_svwrffr
+  // CHECK: call void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1> %op)
+  // CHECK: ret void
+  svwrffr(op);
+}