[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

[Zoe Carver via Phabricator via cfe-commits]

zoecarver updated this revision to Diff 251758.
zoecarver added a comment.

Fix based on review:

- update comments
- return 64 for Core2


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74918/new/

https://reviews.llvm.org/D74918

Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/X86.cpp


Index: clang/lib/Basic/Targets/X86.cpp
===================================================================
--- clang/lib/Basic/Targets/X86.cpp
+++ clang/lib/Basic/Targets/X86.cpp
@@ -1745,7 +1745,7 @@
 // | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
 // | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
 // | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
-// | Bradwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
+// | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
 // | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
 // | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
 // | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |
@@ -1833,11 +1833,11 @@
     case CK_x86_64:
     case CK_Yonah:
     case CK_Penryn:
+    case CK_Core2:
       return 64;
 
     // The following currently have unknown cache line sizes (but they are probably all 64):
     // Core
-    case CK_Core2:
     case CK_Generic:
       return None;
   }
Index: clang/include/clang/Basic/TargetInfo.h
===================================================================
--- clang/include/clang/Basic/TargetInfo.h
+++ clang/include/clang/Basic/TargetInfo.h
@@ -1207,7 +1207,7 @@
   }
 
   // Get the cache line size of a given cpu. This method switches over
-  // the given cpu and returns `0` if the CPU is not found.
+  // the given cpu and returns "None" if the CPU is not found.
   virtual Optional<unsigned> getCPUCacheLineSize() const { return None; }
 
   // Returns maximal number of args passed in registers.


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D74918.251758.patch
Type: text/x-patch
Size: 2886 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/cfe-commits/attachments/20200320/ee13ec0e/attachment.bin>