[clang] 9624beb - [docs] Regenerate ClangCommandLineReference.rst
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Tue Mar 10 11:11:40 PDT 2020
Author: Craig Topper
Date: 2020-03-10T11:10:18-07:00
New Revision: 9624beb38a46037f69362650a52e06d8be4fd006
URL: https://github.com/llvm/llvm-project/commit/9624beb38a46037f69362650a52e06d8be4fd006
DIFF: https://github.com/llvm/llvm-project/commit/9624beb38a46037f69362650a52e06d8be4fd006.diff
LOG: [docs] Regenerate ClangCommandLineReference.rst
Just ran clang-tblgen -gen-opt-docs ClangOptionDocs.td
Added:
Modified:
clang/docs/ClangCommandLineReference.rst
Removed:
################################################################################
diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst
index 5af9d64ae0fc..74e831c36eb9 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -90,7 +90,7 @@ Run the static analyzer
.. option:: --analyzer-output<arg>
-Static analyzer report output format (html\|plist\|plist-multi-file\|plist-html\|text).
+Static analyzer report output format (html\|plist\|plist-multi-file\|plist-html\|sarif\|text).
.. option:: -ansi, --ansi
@@ -122,14 +122,6 @@ Output path for the plist report
.. option:: -bundle\_loader <arg>
.. program:: clang
-.. option:: -cfguard
-
-Emit tables and checks for Windows Control Flow Guard.
-
-.. option:: -cfguard-no-checks
-
-Emit tables required for Windows Control Flow Guard without checks.
-
.. option:: -client\_name<arg>
.. option:: -compatibility\_version<arg>
@@ -200,6 +192,10 @@ Filename (or -) to write dependency output to
Emit Clang AST files for source inputs
+.. option:: -enable-trivial-auto-var-init-zero-knowing-it-will-be-removed-from-clang
+
+Trivial automatic variable initialization to zero is only here for benchmarks, it'll eventually be removed, and I'm OK with that because I'm only using it to benchmark
+
.. option:: -exported\_symbols\_list <arg>
.. option:: -faligned-new=<arg>
@@ -212,10 +208,6 @@ Use approximate transcendental functions
Flush denormal floating point values to zero in CUDA device mode.
-.. option:: -fcuda-rdc, -fno-cuda-rdc
-
-Generate relocatable device code, also known as separate compilation mode.
-
.. option:: -fcuda-short-ptr, -fno-cuda-short-ptr
Use 32-bit pointers for accessing const/local/shared address spaces.
@@ -224,8 +216,20 @@ Use 32-bit pointers for accessing const/local/shared address spaces.
Reserve register r19 (Hexagon only)
+.. option:: -fgpu-allow-device-init, -fno-gpu-allow-device-init
+
+Allow device side init function in HIP
+
+.. option:: -fgpu-rdc, -fcuda-rdc, -fno-gpu-rdc
+
+Generate relocatable device code, also known as separate compilation mode.
+
.. option:: -fheinous-gnu-extensions
+.. option:: -fhip-new-launch-api, -fno-hip-new-launch-api
+
+Use new kernel launching API for HIP.
+
.. option:: -flat\_namespace
.. option:: -fopenmp-targets=<arg1>,<arg2>...
@@ -248,6 +252,14 @@ Specify comma-separated list of triples OpenMP offloading targets to be supporte
Add -rpath with architecture-specific resource directory to the linker flags
+.. option:: -fsanitize-system-blacklist=<arg>
+
+Path to system blacklist file for sanitizers
+
+.. option:: -fsystem-module
+
+Build this module as a system module. Only used with -emit-module
+
.. option:: --gcc-toolchain=<arg>, -gcc-toolchain <arg>
Use the gcc toolchain at the given directory
@@ -256,6 +268,16 @@ Use the gcc toolchain at the given directory
Generate CodeView debug information
+.. option:: -gcodeview-ghash, -gno-codeview-ghash
+
+Emit type record hashes in a .debug$H section
+
+.. option:: -ginline-line-tables, -gno-inline-line-tables
+
+.. option:: --gpu-max-threads-per-block=<arg>
+
+Default max threads per block for kernel launch bounds for HIP
+
.. option:: -headerpad\_max\_install\_names<arg>
.. option:: -help, --help
@@ -270,6 +292,10 @@ Display help for hidden options
Link clang-offload-bundler bundles for HIP
+.. option:: -ibuiltininc
+
+Enable builtin #include directories even when -nostdinc is used before or after -ibuiltininc. Using -nobuiltininc after the option disables it
+
.. option:: -image\_base <arg>
.. option:: -index-header-map
@@ -280,6 +306,8 @@ Make the next included directory (-I or -F) an indexer header map
.. option:: -install\_name <arg>
+.. option:: -interface-stub-version=<arg>
+
.. option:: -keep\_private\_externs
.. option:: -lazy\_framework <arg>
@@ -290,6 +318,10 @@ Make the next included directory (-I or -F) an indexer header map
.. option:: -mbig-endian, -EB
+.. option:: -mbranch-protection=<arg>
+
+Enforce targets of indirect branches and function returns
+
.. option:: --migrate
Run the migrator
@@ -334,12 +366,14 @@ Disable builtin #include directories
.. option:: -nocudainc
-.. option:: -nocudalib
-
.. option:: -nodefaultlibs
.. option:: -nofixprebinding
+.. option:: -nogpulib, -nocudalib
+
+Do not link device library for CUDA/HIP device compilation
+
.. option:: -nolibc
.. option:: -nomultidefs
@@ -594,6 +628,12 @@ Statically link the sanitizer runtime
.. option:: -static-libstdc++
+.. option:: -static-openmp
+
+Use the static host OpenMP runtime while linking.
+
+.. option:: -static-pie
+
.. option:: -std-default=<arg>
.. option:: -stdlib=<arg>, --stdlib=<arg>, --stdlib <arg>
@@ -614,10 +654,6 @@ C++ standard library to use
Generate code for the given target
-.. option:: --print-supported-cpus
-
-Print supported cpu models for the given target
-
.. option:: -time
Time individual commands
@@ -638,6 +674,10 @@ Enable some traditional CPP emulation
.. option:: -unexported\_symbols\_list <arg>
+.. option:: -unwindlib=<arg>, --unwindlib=<arg>
+
+Unwind library to use
+
.. option:: -v, --verbose
Show commands to run and use verbose output
@@ -696,10 +736,18 @@ Only run preprocess and compilation steps
Only run preprocess, compile, and assemble steps
+.. option:: -emit-interface-stubs
+
+Generate Inteface Stub Files.
+
.. option:: -emit-llvm
Use the LLVM representation for assembler and object files
+.. option:: -emit-merged-ifs
+
+Generate Interface Stub Files, emit merged text not binary.
+
.. option:: -fsyntax-only
.. option:: -module-file-info
@@ -800,15 +848,7 @@ Don't use blacklist file for sanitizers
.. option:: -fparse-all-comments
-.. option:: -frecord-command-line, -frecord-gcc-switches, -fno-record-command-line, -fno-record-gcc-switches
-
-Generate a section named ".GCC.command.line" containing the clang driver
-command-line. After linking, the section may contain multiple command lines,
-which will be individually terminated by null bytes. Separate arguments within
-a command line are combined with spaces; spaces and backslashes within an
-argument are escaped with backslashes. This format
diff ers from the format of
-the equivalent section produced by GCC with the -frecord-gcc-switches flag.
-This option is currently only supported on ELF targets.
+.. option:: -frecord-command-line, -fno-record-command-line, -frecord-gcc-switches
.. option:: -fsanitize-address-field-padding=<arg>
@@ -818,24 +858,26 @@ Level of field padding for AddressSanitizer
Enable linker dead stripping of globals in AddressSanitizer
-.. option:: -fsanitize-address-use-odr-indicator, -fno-sanitize-address-use-odr-indicator
-
-Enable ODR indicator globals to avoid false ODR violation reports in partially sanitized programs at the cost of an increase in binary size
-
.. option:: -fsanitize-address-poison-custom-array-cookie, -fno-sanitize-address-poison-custom-array-cookie
-Enable "poisoning" array cookies when allocating arrays with a custom operator new\[\] in Address Sanitizer, preventing accesses to the cookies from user code. An array cookie is a small implementation-defined header added to certain array allocations to record metadata such as the length of the array. Accesses to array cookies from user code are technically allowed by the standard but are more likely to be the result of an out-of-bounds array access.
-
-An operator new\[\] is "custom" if it is not one of the allocation functions provided by the C++ standard library. Array cookies from non-custom allocation functions are always poisoned.
+Enable poisoning array cookies when using custom operator new\[\] in AddressSanitizer
.. option:: -fsanitize-address-use-after-scope, -fno-sanitize-address-use-after-scope
Enable use-after-scope detection in AddressSanitizer
+.. option:: -fsanitize-address-use-odr-indicator, -fno-sanitize-address-use-odr-indicator
+
+Enable ODR indicator globals to avoid false ODR violation reports in partially sanitized programs at the cost of an increase in binary size
+
.. option:: -fsanitize-blacklist=<arg>
Path to blacklist file for sanitizers
+.. option:: -fsanitize-cfi-canonical-jump-tables, -fno-sanitize-cfi-canonical-jump-tables
+
+Make the jump table addresses canonical in the symbol table
+
.. option:: -fsanitize-cfi-cross-dso, -fno-sanitize-cfi-cross-dso
Enable control flow integrity (CFI) checks for cross-DSO calls.
@@ -848,7 +890,13 @@ Generalize pointers in CFI indirect call type signature checks
Specify the type of coverage instrumentation for Sanitizers
-.. option:: -fsanitize-link-c++-runtime
+.. option:: -fsanitize-hwaddress-abi=<arg>
+
+Select the HWAddressSanitizer ABI to target (interceptor or platform, default interceptor). This option is currently unused.
+
+.. option:: -fsanitize-link-c++-runtime, -fno-sanitize-link-c++-runtime
+
+.. option:: -fsanitize-link-runtime, -fno-sanitize-link-runtime
.. option:: -fsanitize-memory-track-origins, -fno-sanitize-memory-track-origins
@@ -904,18 +952,16 @@ Strip (or keep only, if negative) a given number of path components when emittin
Turn on runtime checks for various forms of undefined or suspicious behavior. See user manual for available checks
-.. option:: -fno-semantic-interposition, -fsemantic-interposition
-
-Enable semantic interposition. Semantic interposition allows for the
-interposition of a symbol by another at runtime, thus preventing a range of
-inter-procedural optimisation.
-
.. option:: -moutline, -mno-outline
Enable function outlining (AArch64 only)
.. option:: --param <arg>, --param=<arg>
+.. option:: -print-supported-cpus, --print-supported-cpus, -mcpu=?, -mtune=?
+
+Print supported cpu models for the given target (if target is not specified, it will print the supported cpus for the default target)
+
.. option:: -std=<arg>, --std=<arg>, --std <arg>
Language standard to compile for
@@ -957,6 +1003,10 @@ Pass the comma separated arguments in <arg> to the preprocessor
Pass <arg> to the preprocessor
+.. option:: -fmacro-prefix-map=<arg>
+
+remap file source paths in predefined preprocessor macros
+
Include path management
-----------------------
@@ -1086,10 +1136,20 @@ Set directory to include search path with prefix
Add directory to SYSTEM include search path, absolute paths are relative to -isysroot
+.. option:: --libomptarget-nvptx-path=<arg>
+
+Path to libomptarget-nvptx libraries
+
.. option:: --ptxas-path=<arg>
Path to ptxas (used for compiling CUDA code)
+.. program:: clang1
+.. option:: -stdlib++-isystem<directory>
+.. program:: clang
+
+Use directory as the C++ standard library include path
+
.. option:: --system-header-prefix=<prefix>, --no-system-header-prefix=<prefix>, --system-header-prefix <arg>
Treat all #include paths starting with <prefix> as including a system header.
@@ -1241,6 +1301,10 @@ Use ANSI escape codes for diagnostics
Use Apple's kernel extensions ABI
+.. option:: -fapple-link-rtlib
+
+Force linking the clang builtins runtime library
+
.. option:: -fapple-pragma-pack, -fno-apple-pragma-pack
Enable Apple gcc-compatible #pragma pack handling
@@ -1295,6 +1359,8 @@ Enable C++ static destructor registration (the default)
Instrument control-flow architecture protection. Options: return, branch, full, none.
+.. option:: -fcf-runtime-abi=<arg>
+
.. option:: -fchar8\_t, -fno-char8\_t
Enable C++ builtin type char8\_t
@@ -1307,9 +1373,7 @@ Use colors in diagnostics
.. option:: -fcommon, -fno-common
-Place definitions of variables with no storage class and no initializer
-(tentative definitions) in a common block, instead of generating individual
-zero-initialized definitions (default -fno-common).
+Place uninitialized global variables in a common block
.. option:: -fcompile-resource=<arg>, --resource <arg>, --resource=<arg>
@@ -1323,6 +1387,10 @@ zero-initialized definitions (default -fno-common).
.. option:: -fconstexpr-steps=<arg>
+.. option:: -fconvergent-functions
+
+Assume functions may be convergent
+
.. option:: -fcoroutines-ts, -fno-coroutines-ts
Enable support for the C++ Coroutines TS
@@ -1333,6 +1401,16 @@ Generate coverage mapping to enable code coverage analysis
.. option:: -fcreate-profile
+.. option:: -fcs-profile-generate
+
+Generate instrumented code to collect context sensitive execution counts into default.profraw (overridden by LLVM\_PROFILE\_FILE env var)
+
+.. program:: clang1
+.. option:: -fcs-profile-generate=<directory>
+.. program:: clang
+
+Generate instrumented code to collect context sensitive execution counts into <directory>/default.profraw (overridden by LLVM\_PROFILE\_FILE env var)
+
.. option:: -fcxx-exceptions, -fno-cxx-exceptions
Enable C++ exceptions
@@ -1341,7 +1419,15 @@ Enable C++ exceptions
.. option:: -fdata-sections, -fno-data-sections
-Place each data in its own section (ELF Only)
+Place each data in its own section
+
+.. option:: -fdebug-compilation-dir <arg>, -fdebug-compilation-dir=<arg>
+
+The compilation directory to embed in the debug info.
+
+.. option:: -fdebug-default-version=<arg>
+
+Default DWARF version to use, if a -g option caused DWARF debug info to be produced
.. option:: -fdebug-info-for-profiling, -fno-debug-info-for-profiling
@@ -1359,6 +1445,10 @@ Emit macro debug information
remap file source paths in debug info
+.. option:: -fdebug-ranges-base-address, -fno-debug-ranges-base-address
+
+Use DWARF base address selection entries in debug\_ranges
+
.. option:: -fdebug-types-section, -fno-debug-types-section
Place debug types in their own section (ELF Only)
@@ -1449,12 +1539,20 @@ Enable support for exception handling
.. option:: -fexec-charset=<arg>
+.. option:: -fexperimental-new-constant-interpreter
+
+Enable the experimental new constant interpreter
+
.. option:: -fextdirs=<arg>, --extdirs <arg>, --extdirs=<arg>
.. option:: -ffast-math, -fno-fast-math
Allow aggressive, lossy floating-point optimizations
+.. option:: -ffile-prefix-map=<arg>
+
+remap file source paths in debug info and predefined preprocessor macros
+
.. option:: -ffinite-math-only, -fno-finite-math-only
.. option:: -ffixed-point, -fno-fixed-point
@@ -1463,6 +1561,10 @@ Enable fixed point types
.. option:: -ffor-scope, -fno-for-scope
+.. option:: -fforce-dwarf-frame, -fno-force-dwarf-frame
+
+Always emit a debug frame section
+
.. option:: -fforce-emit-vtables, -fno-force-emit-vtables
Emits more virtual tables to improve devirtualization
@@ -1473,7 +1575,15 @@ Enable support for int128\_t type
.. option:: -ffp-contract=<arg>
-Form fused FP ops (e.g. FMAs): fast (everywhere) \| on (according to FP\_CONTRACT pragma, default) \| off (never fuse)
+Form fused FP ops (e.g. FMAs): fast (everywhere) \| on (according to FP\_CONTRACT pragma) \| off (never fuse). Default is 'fast' for CUDA/HIP and 'on' otherwise.
+
+.. option:: -ffp-exception-behavior=<arg>
+
+Specifies the exception behavior of floating-point operations.
+
+.. option:: -ffp-model=<arg>
+
+Controls the semantics of floating-point calculations.
.. option:: -ffreestanding
@@ -1481,7 +1591,7 @@ Assert that the compilation takes place in a freestanding environment
.. option:: -ffunction-sections, -fno-function-sections
-Place each function in its own section (ELF Only)
+Place each function in its own section
.. option:: -fgnu-inline-asm, -fno-gnu-inline-asm
@@ -1497,12 +1607,20 @@ Generate output compatible with the standard GNU Objective-C runtime
Use the gnu89 inline semantics
+.. option:: -fgnuc-version=<arg>
+
+Sets various macros to claim compatibility with the given GCC version (default is 4.2.1)
+
.. option:: -fhonor-infinities, -fhonor-infinites, -fno-honor-infinities
.. option:: -fhonor-nans, -fno-honor-nans
.. option:: -fhosted
+.. option:: -fignore-exceptions
+
+Enable support for ignoring exception handling constructs
+
.. option:: -fimplicit-module-maps, -fmodule-maps, -fno-implicit-module-maps
Implicitly search the file system for module map files.
@@ -1527,13 +1645,19 @@ Like -finstrument-functions, but insert the calls after inlining
Enable the integrated assembler
+.. option:: -fintegrated-cc1, -fno-integrated-cc1
+
+Run cc1 in-process
+
.. option:: -fjump-tables, -fno-jump-tables
.. option:: -fkeep-static-consts
Keep static const variables even if unused
-.. option:: -flax-vector-conversions, -fno-lax-vector-conversions
+.. option:: -flax-vector-conversions=<arg>, -flax-vector-conversions (equivalent to -flax-vector-conversions=integer), -fno-lax-vector-conversions (equivalent to -flax-vector-conversions=none)
+
+Enable implicit vector bit-casts
.. option:: -flimited-precision=<arg>
@@ -1557,6 +1681,10 @@ Set LTO mode to either 'full' or 'thin'
Require math functions to indicate errors by setting errno
+.. option:: -fmax-tokens=<arg>
+
+Max total number of preprocessed tokens for -Wmax-tokens.
+
.. option:: -fmax-type-align=<arg>
Specify the maximum alignment to enforce on pointers lacking an explicit alignment
@@ -1601,6 +1729,10 @@ Like -fmodules-decluse but requires all headers to be in modules
Enable support for the C++ Modules TS
+.. option:: -fmodules-validate-input-files-content
+
+Validate PCM input files based on content if mtime
diff ers
+
.. option:: -fms-compatibility, -fno-ms-compatibility
Enable full Microsoft Visual C++ compatibility
@@ -1615,7 +1747,7 @@ Accept some non-standard constructs supported by the Microsoft compiler
.. option:: -fms-memptr-rep=<arg>
-.. option:: -fms-volatile<arg>
+.. option:: -fms-volatile
.. option:: -fmsc-version=<arg>
@@ -1653,8 +1785,24 @@ Control emission of RTTI data
.. option:: -fno-strict-modules-decluse
+.. option:: -fno-temp-file
+
+Directly create compilation output files. This may lead to incorrect incremental builds if the compiler crashes
+
+.. option:: -fno-virtual-function\_elimination
+
.. option:: -fno-working-directory
+.. option:: -fno\_modules-validate-input-files-content
+
+.. program:: clang1
+.. option:: -fno\_pch-validate-input-files-content
+.. program:: clang
+
+.. option:: -fnostack-clash-protection
+
+Disable stack clash protection
+
.. option:: -fnoxray-link-deps
.. option:: -fobjc-abi-version=<arg>
@@ -1667,6 +1815,8 @@ Synthesize retain and release calls for Objective-C pointers
Use EH-safe code when synthesizing retains and releases in -fobjc-arc
+.. option:: -fobjc-convert-messages-to-runtime-calls, -fno-objc-convert-messages-to-runtime-calls
+
.. option:: -fobjc-exceptions, -fno-objc-exceptions
Enable Objective-C exceptions
@@ -1711,8 +1861,7 @@ Emit OpenMP code only for SIMD-based constructs.
.. option:: -foptimization-record-file=<file>
-Implies -fsave-optimization-record. On Darwin platforms, this
- cannot be used with multiple -arch <arch> options.
+Specify the output name of the file containing the optimization remarks. Implies -fsave-optimization-record. On Darwin platforms, this cannot be used with multiple -arch <arch> options.
.. option:: -foptimization-record-passes=<regex>
@@ -1720,6 +1869,10 @@ Only include passes which match a specified regular expression in the generated
.. option:: -foptimize-sibling-calls, -fno-optimize-sibling-calls
+.. option:: -forder-file-instrumentation
+
+Generate instrumented code to collect order file into default.profraw file (overridden by '=' form of option or LLVM\_PROFILE\_FILE env var)
+
.. option:: -foutput-class-dir=<arg>, --output-class-directory <arg>, --output-class-directory=<arg>
.. option:: -fpack-struct, -fno-pack-struct
@@ -1734,12 +1887,24 @@ Specify the default maximum struct packing alignment
Recognize and construct Pascal-style string literals
+.. option:: -fpass-plugin=<dsopath>
+
+Load pass plugin from a dynamic shared object file (only with new pass manager).
+
+.. option:: -fpatchable-function-entry=<N,M>
+
+Generate M NOPs before function entry and N-M NOPs after function entry
+
.. option:: -fpcc-struct-return
Override the default ABI to return all structs on the stack
.. option:: -fpch-preprocess
+.. option:: -fpch-validate-input-files-content
+
+Validate PCH input files based on content if mtime
diff ers
+
.. option:: -fpic, -fno-pic
.. option:: -fpie, -fno-pie
@@ -1758,6 +1923,14 @@ Load the named plugin (dynamic shared object)
.. option:: -fprofile-dir=<arg>
+.. option:: -fprofile-exclude-files=<arg>
+
+Instrument only functions from files where names don't match all the regexes separated by a semi-colon
+
+.. option:: -fprofile-filter-files=<arg>
+
+Instrument only functions from files where names match any regex separated by a semi-colon
+
.. option:: -fprofile-generate, -fno-profile-generate
Generate instrumented code to collect execution counts into default.profraw (overridden by LLVM\_PROFILE\_FILE env var)
@@ -1786,6 +1959,10 @@ Generate instrumented code to collect execution counts into <file> (overridden b
Use instrumentation data for profile-guided optimization
+.. option:: -fprofile-remapping-file=<file>, -fprofile-remapping-file <arg>
+
+Use the remappings described in <file> to match the profile data against names in the program
+
.. option:: -fprofile-sample-accurate, -fauto-profile-accurate, -fno-profile-sample-accurate
Specifies that the sample profile is accurate. If the sample
@@ -1841,6 +2018,8 @@ Turn on loop reroller
.. option:: -fropi, -fno-ropi
+.. option:: -frounding-math, -fno-rounding-math
+
.. option:: -frtti, -fno-rtti
.. option:: -frwpi, -fno-rwpi
@@ -1853,12 +2032,14 @@ Generate a YAML optimization record file
.. option:: -fsave-optimization-record=<format>
.. program:: clang
-Generate an optimization record file in a specific format.
+Generate an optimization record file in a specific format
.. option:: -fseh-exceptions
Use SEH style exceptions
+.. option:: -fsemantic-interposition, -fno-semantic-interposition
+
.. option:: -fshort-enums, -fno-short-enums
Allocate to an enum type only as many bytes as it needs for the declared range of possible values
@@ -1903,28 +2084,32 @@ Enable the superword-level parallelism vectorization passes
Provide minimal debug info in the object/executable to facilitate online symbolication/stack traces in the absence of .dwo/.dwp files when using Split DWARF
+.. option:: -fsplit-lto-unit, -fno-split-lto-unit
+
+Enables splitting of the LTO unit.
+
.. option:: -fsplit-stack
+.. option:: -fstack-clash-protection
+
+Enable stack clash protection
+
.. option:: -fstack-protector, -fno-stack-protector
-Enable stack protectors for functions potentially vulnerable to stack smashing
+Enable stack protectors for some functions vulnerable to stack smashing. This uses a loose heuristic which considers functions vulnerable if they contain a char (or 8bit integer) array or constant sized calls to alloca, which are of greater size than ssp-buffer-size (default: 8 bytes). All variable sized calls to alloca are considered vulnerable
.. option:: -fstack-protector-all
-Force the usage of stack protectors for all functions
+Enable stack protectors for all functions
.. option:: -fstack-protector-strong
-Use a strong heuristic to apply stack protectors to functions
+Enable stack protectors for some functions vulnerable to stack smashing. Compared to -fstack-protector, this uses a stronger heuristic that includes functions containing arrays of any size (and any type), as well as any calls to alloca or the taking of an address from a local variable
.. option:: -fstack-size-section, -fno-stack-size-section
Emit section containing metadata on function stack sizes
-.. option:: -fstack-clash-protection, -fno-stack-clash-protection
-
-Instrument stack allocation to prevent stack clash attacks (x86, non-Windows only).
-
.. option:: -fstandalone-debug, -fno-limit-debug-info, -fno-standalone-debug
Emit full debug info for all types used by the program
@@ -1951,6 +2136,8 @@ Enable optimizations based on the strict rules for overwriting polymorphic C++ o
.. option:: -fstruct-path-tbaa, -fno-struct-path-tbaa
+.. option:: -fsymbol-partition=<arg>
+
.. option:: -ftabstop=<arg>
.. option:: -ftemplate-backtrace-limit=<arg>
@@ -1961,6 +2148,10 @@ Enable optimizations based on the strict rules for overwriting polymorphic C++ o
.. option:: -ftest-coverage
+.. option:: -fthin-link-bitcode=<arg>
+
+Write minimized bitcode to <file> for the ThinLTO thin link only
+
.. option:: -fthinlto-index=<arg>
Perform ThinLTO importing using provided function summary index
@@ -1971,8 +2162,10 @@ Perform ThinLTO importing using provided function summary index
.. option:: -ftime-trace
-Turn on time profiler. Results can be analyzed with chrome://tracing or
-`Speedscope App <https://www.speedscope.app>`_ for flamegraph visualization
+
+Turn on time profiler. Generates JSON file based on output filename. Results
+can be analyzed with chrome://tracing or `Speedscope App
+<https://www.speedscope.app>`_ for flamegraph visualization.
.. option:: -ftime-trace-granularity=<arg>
@@ -2002,9 +2195,13 @@ Specify the function to be called on overflow
Process trigraph sequences
+.. option:: -ftrivial-auto-var-init=<arg>
+
+Initialize trivial automatic stack variables: uninitialized (default) \| pattern
+
.. option:: -funique-section-names, -fno-unique-section-names
-Use unique names for text and data sections (ELF Only)
+Use unique names for text and data sections
.. option:: -funit-at-a-time, -fno-unit-at-a-time
@@ -2030,6 +2227,10 @@ Use .init\_array instead of .ctors
.. option:: -fuse-line-directives, -fno-use-line-directives
+.. option:: -fvalidate-ast-input-files-content
+
+Compute and store the hash of input files used to build an AST. Files with mismatching mtime's are considered valid if both contents is identical
+
.. option:: -fveclib=<arg>
Use the given vector functions library
@@ -2038,7 +2239,15 @@ Use the given vector functions library
Enable the loop vectorization passes
-.. option:: -fverbose-asm, -fno-verbose-asm, -dA
+.. option:: -fverbose-asm, -dA, -fno-verbose-asm
+
+.. option:: -fvirtual-function-elimination
+
+Enables dead virtual function elimination optimization. Requires -flto=full
+
+.. option:: -fvisibility-global-new-delete-hidden
+
+Give global C++ operator new and delete declarations hidden visibility
.. option:: -fvisibility-inlines-hidden
@@ -2052,6 +2261,10 @@ Give global types 'default' visibility and global functions and variables 'hidde
Set the default symbol visibility for all global declarations
+.. option:: -fwasm-exceptions
+
+Use WebAssembly style exceptions
+
.. option:: -fwhole-program-vtables, -fno-whole-program-vtables
Enables whole-program vtable optimization. Requires -flto
@@ -2080,6 +2293,10 @@ DEPRECATED: Filename defining the whitelist for imbuing the 'always instrument'
Filename defining the list of functions/types for imbuing XRay attributes.
+.. option:: -fxray-ignore-loops, -fno-xray-ignore-loops
+
+Don't instrument functions with loops unless they also meet the minimum function size
+
.. option:: -fxray-instruction-threshold<arg>
.. program:: clang1
@@ -2094,7 +2311,7 @@ Generate XRay instrumentation sleds on function entry and exit
.. option:: -fxray-instrumentation-bundle=<arg>
-Select which XRay instrumentation points to emit. Options: all, none, function, custom. Default is 'all'.
+Select which XRay instrumentation points to emit. Options: all, none, function-entry, function-exit, function, custom. Default is 'all'. 'function' includes both 'function-entry' and 'function-exit'.
.. option:: -fxray-link-deps
@@ -2172,12 +2389,146 @@ OpenCL only. Defines that the global work-size be a multiple of the work-group s
OpenCL only. Allow unsafe floating-point optimizations. Also implies -cl-no-signed-zeros and -cl-mad-enable.
+SYCL flags
+----------
+.. option:: -fsycl, -fno-sycl
+
+Enable SYCL kernels compilation for device
+
+.. option:: -sycl-std=<arg>
+
+SYCL language standard to compile for.
+
Target-dependent compilation options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. option:: -G<size>, -G=<arg>, -msmall-data-threshold=<arg>
Put objects of at most <size> bytes into small data section (MIPS / Hexagon)
+.. option:: -ffixed-x1
+
+Reserve the 1 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x10
+
+Reserve the 10 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x11
+
+Reserve the 11 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x12
+
+Reserve the 12 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x13
+
+Reserve the 13 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x14
+
+Reserve the 14 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x15
+
+Reserve the 15 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x16
+
+Reserve the 16 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x17
+
+Reserve the 17 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x18
+
+Reserve the 18 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x19
+
+Reserve the 19 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x2
+
+Reserve the 2 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x20
+
+Reserve the 20 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x21
+
+Reserve the 21 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x22
+
+Reserve the 22 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x23
+
+Reserve the 23 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x24
+
+Reserve the 24 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x25
+
+Reserve the 25 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x26
+
+Reserve the 26 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x27
+
+Reserve the 27 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x28
+
+Reserve the 28 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x29
+
+Reserve the 29 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x3
+
+Reserve the 3 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x30
+
+Reserve the 30 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x31
+
+Reserve the 31 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x4
+
+Reserve the 4 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x5
+
+Reserve the 5 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x6
+
+Reserve the 6 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x7
+
+Reserve the 7 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x8
+
+Reserve the 8 register (AArch64/RISC-V only)
+
+.. option:: -ffixed-x9
+
+Reserve the 9 register (AArch64/RISC-V only)
+
.. option:: -m16
.. option:: -m32
@@ -2186,6 +2537,16 @@ Put objects of at most <size> bytes into small data section (MIPS / Hexagon)
.. option:: -mabi=<arg>
+.. option:: -malign-branch-boundary=<arg>
+
+Specify the boundary's size to align branches
+
+.. option:: -malign-branch-prefix-size=<arg>
+
+.. option:: -malign-branch=<arg1>,<arg2>...
+
+Specify types of branches to align
+
.. option:: -malign-double
Align doubles to two words in structs (x86 only)
@@ -2198,13 +2559,17 @@ Align doubles to two words in structs (x86 only)
Link stack frames through backchain on System Z
-.. option:: -mcmodel=<arg>
+.. option:: -mbranches-within-32B-boundaries
-.. option:: -mconsole<arg>
+Align selected branches (fused, jcc, jmp) within 32-byte boundary
-.. option:: -mcpu=<arg>, -mv5 (equivalent to -mcpu=hexagonv5), -mv55 (equivalent to -mcpu=hexagonv55), -mv60 (equivalent to -mcpu=hexagonv60), -mv62 (equivalent to -mcpu=hexagonv62), -mv65 (equivalent to -mcpu=hexagonv65)
+.. option:: -mcmodel=<arg>, -mcmodel=medany (equivalent to -mcmodel=medium), -mcmodel=medlow (equivalent to -mcmodel=small)
-Use -mcpu=? to see a list of supported cpu models.
+.. option:: -mconsole<arg>
+
+.. program:: clang1
+.. option:: -mcpu=<arg>, -mv5 (equivalent to -mcpu=hexagonv5), -mv55 (equivalent to -mcpu=hexagonv55), -mv60 (equivalent to -mcpu=hexagonv60), -mv62 (equivalent to -mcpu=hexagonv62), -mv65 (equivalent to -mcpu=hexagonv65), -mv66 (equivalent to -mcpu=hexagonv66), -mv67 (equivalent to -mcpu=hexagonv67), -mv67t (equivalent to -mcpu=hexagonv67t)
+.. program:: clang
.. option:: -mcrc, -mno-crc
@@ -2238,6 +2603,8 @@ Enable merging of globals
.. option:: -mhwdiv=<arg>, --mhwdiv <arg>, --mhwdiv=<arg>
+.. option:: -mhwmult=<arg>
+
.. option:: -miamcu, -mno-iamcu
Use Intel MCU ABI
@@ -2260,7 +2627,7 @@ Generate branches with extended addressability, usually via indirect jumps.
.. option:: -mmacosx-version-min=<arg>, -mmacos-version-min=<arg>
-Set macOS deployment target
+Set Mac OS X deployment target
.. option:: -mmcu=<arg>
@@ -2268,12 +2635,20 @@ Set macOS deployment target
Set the default structure layout to be compatible with the Microsoft compiler standard
+.. option:: -mnop-mcount
+
+Generate mcount/\_\_fentry\_\_ calls as nops. To activate they need to be patched in.
+
.. option:: -momit-leaf-frame-pointer, -mno-omit-leaf-frame-pointer
Omit frame pointer setup for leaf functions
.. option:: -moslib=<arg>
+.. option:: -mpacked-stack, -mno-packed-stack
+
+Use packed stack layout (SystemZ only).
+
.. option:: -mpie-copy-relocations, -mno-pie-copy-relocations
Use copy relocations support for PIE builds
@@ -2292,6 +2667,10 @@ Enable hexagon-qdsp6 backward compatibility
.. option:: -mrecip=<arg1>,<arg2>...
.. program:: clang
+.. option:: -mrecord-mcount
+
+Generate a \_\_mcount\_loc section entry for each \_\_fentry\_\_ call.
+
.. option:: -mred-zone, -mno-red-zone
.. option:: -mregparm=<arg>
@@ -2314,6 +2693,8 @@ Select return address signing scope
Use software floating point
+.. option:: -mspeculative-load-hardening, -mno-speculative-load-hardening
+
.. option:: -mstack-alignment=<arg>
Set the stack alignment
@@ -2338,9 +2719,17 @@ The thread model to use, e.g. posix, single (posix by default)
.. option:: -mthumb, -mno-thumb
-.. option:: -mtune=<arg>
+.. option:: -mtls-direct-seg-refs, -mno-tls-direct-seg-refs
-Use -mtune=? to see a list of supported cpu models.
+Enable direct TLS access through segment registers (default)
+
+.. option:: -mtls-size=<arg>
+
+Specify bit size of immediate TLS offsets (AArch64 ELF only): 12 (for 4KB) \| 24 (for 16MB, default) \| 32 (for 4GB) \| 48 (for 256TB, needs -mcmodel=large)
+
+.. program:: clang1
+.. option:: -mtune=<arg>
+.. program:: clang
.. option:: -mtvos-version-min=<arg>, -mappletvos-version-min=<arg>
@@ -2352,56 +2741,16 @@ Use -mtune=? to see a list of supported cpu models.
.. option:: -mwatchos-version-min=<arg>
+.. option:: -mwavefrontsize64, -mno-wavefrontsize64
+
+Wavefront size 64 is used
+
.. option:: -mwindows<arg>
.. option:: -mx32
AARCH64
-------
-.. option:: -ffixed-x1
-
-Reserve the x1 register (AArch64 only)
-
-.. option:: -ffixed-x2
-
-Reserve the x2 register (AArch64 only)
-
-.. option:: -ffixed-x3
-
-Reserve the x3 register (AArch64 only)
-
-.. option:: -ffixed-x4
-
-Reserve the x4 register (AArch64 only)
-
-.. option:: -ffixed-x5
-
-Reserve the x5 register (AArch64 only)
-
-.. option:: -ffixed-x6
-
-Reserve the x6 register (AArch64 only)
-
-.. option:: -ffixed-x7
-
-Reserve the x7 register (AArch64 only)
-
-.. option:: -ffixed-x18
-
-Reserve the x18 register (AArch64 only)
-
-.. option:: -ffixed-x20
-
-Reserve the x20 register (AArch64 only)
-
-.. option:: -fcall-saved-x8
-
-Make the x8 register call-saved (AArch64 only)
-
-.. option:: -fcall-saved-x9
-
-Make the x9 register call-saved (AArch64 only)
-
.. option:: -fcall-saved-x10
Make the x10 register call-saved (AArch64 only)
@@ -2430,6 +2779,14 @@ Make the x15 register call-saved (AArch64 only)
Make the x18 register call-saved (AArch64 only)
+.. option:: -fcall-saved-x8
+
+Make the x8 register call-saved (AArch64 only)
+
+.. option:: -fcall-saved-x9
+
+Make the x9 register call-saved (AArch64 only)
+
.. option:: -mfix-cortex-a53-835769, -mno-fix-cortex-a53-835769
Workaround Cortex-A53 erratum 835769 (AArch64 only)
@@ -2440,14 +2797,17 @@ Generate code which only uses the general purpose registers (AArch64 only)
AMDGPU
------
+.. option:: -mcode-object-v3, -mno-code-object-v3
+
+Enable code object v3 (AMDGPU only)
+
.. option:: -mcumode, -mno-cumode
-CU wavefront execution mode is used if enabled and WGP wavefront execution mode
-is used if disabled (AMDGPU only)
+CU wavefront execution mode is used (AMDGPU only)
-.. option:: -mwavefrontsize64, -mno-wavefrontsize64
+.. option:: -msram-ecc, -mno-sram-ecc
-Wavefront size 64 is used if enabled and wavefront size 32 if disabled (AMDGPU only)
+Enable SRAM ECC (AMDGPU only)
.. option:: -mxnack, -mno-xnack
@@ -2455,154 +2815,22 @@ Enable XNACK (AMDGPU only)
ARM
---
+.. option:: -fAAPCSBitfieldLoad
+
+Follows the AAPCS standard that all volatile bit-field write generates at least one load. (ARM only).
+
.. option:: -ffixed-r9
Reserve the r9 register (ARM only)
-.. option:: -march=<name>[+<extension>...]
-
-Specify the target Arm ISA.
-
-The list of accepted architecture names is as follows:
-``armv2``, ``armv2a``,
-``armv3``, ``armv3m``,
-``armv4``, ``armv4t``,
-``armv5t``, ``armv5te``,
-``armv6``, ``armv6k``, ``armv6t2``, ``armv6kz``, ``armv6-m``,
-``armv7-a``, ``armv7ve``, ``armv7-r``, ``armv7-m``, ``armv7e-m``,
-``armv8-a``, ``armv8.1-a``, ``armv8.2-a``, ``armv8.3-a``, ``armv8.5-a``, ``armv8-r``,
-``armv8-m.base``, ``armv8-m.main``, ``armv8.1-m.main``,
-``iwmmxt``,
-``iwmmxt2``,
-``xscale``,
-``armv7s``,
-``armv7k``
-
-Extension modifiers can be used to enable optional architecture features. The
-syntax ``+no``<extension> can be used to disable previously enabled features.
-
-Some of the extension names are generic, but have an architecture specific
-effect. For example, the extension syntax ``+fp`` might enable FPv4-SP-D16 for
-the Armv7-M architecture, but VFPv3-D16 for the Armv7-A arrchitecture.
-
-The following extension names are recognised:
-
-``+crc``
- Enable Cyclic Redundancy Check instructions
-``+crypto``
- Enable cryptographic instructions
-``+sha2``
- Enable SHA1 and SHA256 support instructions
-``+aes``
- Enable AES support instructions
-``+dotprod``
- Enable dot product instructions
-``+dsp``
- Enable digital signal processing (DSP) instructions in ARM and Thumb2
-``+fp``
- Enable floating-point instructions for the baseline FPU implementation
- available for the given architecture
-``+fp.dp``
- Enable optional double-precision floating-point instructions
-``+mve``
- Enable integer-only MVE instructions. This extension also implicitly enables
- the DSP extension.
-``+mve.fp``
- Enable floating-point MVE instructions. This extension also implicitly
- enables the MVE, DSP, FP16, and FPv5-sp-d16 extensions.
-``+idiv``
- Enables the interget divide instructions in ARM and Thumb2
-``+mp``
- Enabled the Multiprocessing extension
-``+simd``
- Enables the baseline SIMD instructions for the given architecture
-``+sec``
- Enable TrustZone security extension
-``+virt``
- Enable Viritualization extensions
-``+fp16``
- Enable half-precision floating-point instructions
-``+ras``
- Enable Reliability, Availability, and Serviceability extensions
-``+fp16fml``
- Enable half-precision floating-point fused multiply-add/sub instructions
-``+sb``
- Enable v8.5a Speculation Barrier
-``+lob``
- Enable Low Overhead Branch extensions
+.. option:: -mcmse
+
+Allow use of CMSE (Armv8-M Security Extensions)
.. option:: -mexecute-only, -mno-execute-only, -mpure-code
Disallow generation of data access to code sections (ARM only)
-.. option:: -mfpu=<name>
-
-Specify floating-point unit (or lack thereof) that is available on the target.
-
-The accepted values for <name> are:
-
-``none``
- Prevent the compiler from using floating-point instructions.
-``vfp``
-
-``vfpv2``
- Enable VFPv2 instructions. Disable the Advanced SIMD extension.
-``vfpv3``
- Enable VFPv3 instructions. Disable the Advanced SIMD extension.
-``vfpv3-fp16``
- Enable VFPv3 instructions, including optional half-precision instructions.
- Disable the Advanced SIMD extension.
-``vfpv3-d16``
- Enable VFPv3 instructions, with access to only 16 double-precision
- registers. Disable the Advanced SIMD extension.
-``vfpv3-d16-fp16``
- Enable VFPv3 instructions, including optional half-precision instructions,
- with access to only 16 double-precision registers. Disable the Advanced
- SIMD extension.
-``vfpv3xd``
- Enable VFPv3 insructions, with single-precision floating-point operations
- only and just 16 double-precision registers. Disable the Advanced SIMD
- extension.
-``vfpv3xd-fp16``
- Enable VFPv3 instructions, with single-precision and half-precision,
- floating-point operations only. Disable the Advanced SIMD extension.
-``vfpv4``
- Enable VFPv4 instructions. Disable the Advanced SIMD extension.
-``vfpv4-d16``
- Enable VFPv4 instructions, with access to only 16 double-precision
- registers. Disable the Advanced SIMD extension.
-``fpv4-sp-d16``
- Enable the Armv7-M FPv4-SP-D16 floating-point extension, with
- single-precision floating-point operations only, and only 16
- double-precision registers.
-``fpv5-d16``
- Enable the Armv7-M FPv5-D16 floating-point extension, with only 16
- double-precision registers.
-``fpv5-sp-d16``
- Enable the Armv7-M FPv5-SP-D16 floating-point extension, with
- single-precision floating-point operations only, and only 16
- double-precision registers.
-``fp-armv8``
- Enable Armv8 floaing-point extension. Disable the cryptographic extension
- and the Advanced SIMD extension.
-``fp-armv8-fullfp16-d16``
- Enable Armv8 floaing-point extension, with half-precision operations and
- only 16 double-precision registers.
-``fp-armv8-fullfp16-sp-d16``
- Enable Armv8 floaing-point extension with only single- and half-precision
- operations and only 16 double-precision registers.
-``neon``
- Enable VFPv3 and Advanced SIMD extensions.
-``neon-fp16``
- Enable VFPv3, Advanced SIMD extensions, and half-precision instructions.
-``neon-vfpv4``
- Enable VFPv4 and Advanced SIMD extensions.
-``neon-fp-armv8``
- Enable Armv8 floaing-point and Advanced SIMD extensions.
-``crypto-neon-fp-armv8``
- Enable the Armv8 floaing-point extension, the cryptographic extension, and
- the Advanced SIMD extension.
-
.. option:: -mno-movt
Disallow use of movt/movw pairs (ARM only)
@@ -2621,7 +2849,7 @@ Disallow generation of deprecated IT blocks for ARMv8. It is on by default for A
.. option:: -mtp=<arg>
-Read thread pointer from coprocessor register (ARM only)
+Thread pointer access method (AArch32/AArch64 only)
.. option:: -munaligned-access, -mno-unaligned-access
@@ -2775,18 +3003,34 @@ PowerPC
.. option:: -msecure-plt
+.. option:: -mspe, -mno-spe
+
.. option:: -mvsx, -mno-vsx
WebAssembly
-----------
+.. option:: -matomics, -mno-atomics
+
+.. option:: -mbulk-memory, -mno-bulk-memory
+
.. option:: -mexception-handling, -mno-exception-handling
+.. option:: -mmultivalue, -mno-multivalue
+
+.. option:: -mmutable-globals, -mno-mutable-globals
+
.. option:: -mnontrapping-fptoint, -mno-nontrapping-fptoint
+.. option:: -mreference-types, -mno-reference-types
+
.. option:: -msign-ext, -mno-sign-ext
.. option:: -msimd128, -mno-simd128
+.. option:: -mtail-call, -mno-tail-call
+
+.. option:: -munimplemented-simd128, -mno-unimplemented-simd128
+
X86
---
.. option:: -m3dnow, -mno-3dnow
@@ -2801,10 +3045,10 @@ X86
.. option:: -mavx2, -mno-avx2
-.. option:: -mavx512bitalg, -mno-avx512bitalg
-
.. option:: -mavx512bf16, -mno-avx512bf16
+.. option:: -mavx512bitalg, -mno-avx512bitalg
+
.. option:: -mavx512bw, -mno-avx512bw
.. option:: -mavx512cd, -mno-avx512cd
@@ -2873,8 +3117,6 @@ X86
.. option:: -mmovdiri, -mno-movdiri
-.. option:: -mmpx, -mno-mpx
-
.. option:: -mmwaitx, -mno-mwaitx
.. option:: -mpclmul, -mno-pclmul
@@ -2931,6 +3173,8 @@ X86
.. option:: -mvpclmulqdq, -mno-vpclmulqdq
+.. option:: -mvzeroupper, -mno-vzeroupper
+
.. option:: -mwaitpkg, -mno-waitpkg
.. option:: -mwbnoinvd, -mno-wbnoinvd
@@ -2953,6 +3197,26 @@ RISCV
Enable linker relaxation
+.. option:: -msave-restore, -mno-save-restore
+
+Enable using library calls for save and restore
+
+Long double flags
+-----------------
+Selects the long double implementation
+
+.. option:: -mlong-double-128
+
+Force long double to be 128 bits
+
+.. option:: -mlong-double-64
+
+Force long double to be 64 bits
+
+.. option:: -mlong-double-80
+
+Force long double to be 80 bits, padded to 128 bits for storage
+
Optimization level
~~~~~~~~~~~~~~~~~~
@@ -2974,6 +3238,10 @@ Kind and level of debug information
Generate source-level debug information
+.. option:: -gdwarf
+
+Generate source-level debug information with the default dwarf version
+
.. option:: -gdwarf-2
Generate source-level debug information with dwarf version 2
@@ -2982,7 +3250,7 @@ Generate source-level debug information with dwarf version 2
Generate source-level debug information with dwarf version 3
-.. option:: -gdwarf-4, -gdwarf
+.. option:: -gdwarf-4
Generate source-level debug information with dwarf version 4
@@ -3010,6 +3278,10 @@ ___________
.. option:: -ggdb3
+.. option:: -gline-directives-only
+
+Emit debug line info directives only
+
.. option:: -gline-tables-only, -g1, -gmlt
Emit debug line number tables only
@@ -3040,10 +3312,16 @@ Embed source text in DWARF debug sections
.. option:: -gpubnames, -gno-pubnames
-.. option:: -grecord-command-line, -grecord-gcc-switches, -gno-record-command-line, -gno-record-gcc-switches
+.. option:: -grecord-command-line, -gno-record-command-line, -grecord-gcc-switches
.. option:: -gsplit-dwarf
+.. program:: clang1
+.. option:: -gsplit-dwarf=<arg>
+.. program:: clang
+
+Set DWARF fission mode to either 'split' or 'single'
+
.. option:: -gstrict-dwarf, -gno-strict-dwarf
.. option:: -gz
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