[PATCH] D72932: [ARM] Follow AACPS standard for volatile bit-fields access width

[Diogo N. Sampaio via Phabricator via cfe-commits]

dnsampaio updated this revision to Diff 242823.
dnsampaio added a comment.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.



- Removed test
- Added clear at the end of run as well, to clear waste
- Moved clearing to a more sensible position


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72932/new/

https://reviews.llvm.org/D72932

Files:
  llvm/lib/CodeGen/TypePromotion.cpp


Index: llvm/lib/CodeGen/TypePromotion.cpp
===================================================================
--- llvm/lib/CodeGen/TypePromotion.cpp
+++ llvm/lib/CodeGen/TypePromotion.cpp
@@ -847,8 +847,7 @@
 
   // Iterate through, and add to, a tree of operands and users in the use-def.
   while (!WorkList.empty()) {
-    Value *V = WorkList.back();
-    WorkList.pop_back();
+    Value *V = WorkList.pop_back_val();
     if (CurrentVisited.count(V))
       continue;
 
@@ -917,7 +916,7 @@
      ++ToPromote;
    }
 
-  // DAG optimisations should be able to handle these cases better, especially
+  // DAG optimizations should be able to handle these cases better, especially
   // for function arguments.
   if (ToPromote < 2 || (Blocks.size() == 1 && (NonFreeArgs > SafeWrap.size())))
     return false;
@@ -941,6 +940,9 @@
   if (!TPC)
     return false;
 
+  AllVisited.clear();
+  SafeToPromote.clear();
+  SafeWrap.clear();
   bool MadeChange = false;
   const DataLayout &DL = F.getParent()->getDataLayout();
   const TargetMachine &TM = TPC->getTM<TargetMachine>();
@@ -998,6 +1000,10 @@
   if (MadeChange)
     LLVM_DEBUG(dbgs() << "After TypePromotion: " << F << "\n");
 
+  AllVisited.clear();
+  SafeToPromote.clear();
+  SafeWrap.clear();
+
   return MadeChange;
 }
 


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