[PATCH] D72218: [clang-tidy] new altera kernel name restriction check

[Eugene Zelenko via Phabricator via cfe-commits]

Eugene.Zelenko added inline comments.


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Comment at: clang-tidy/altera/KernelNameRestrictionCheck.cpp:21
+namespace {
+class KernelNameRestrictionPPCallbacks : public PPCallbacks {
+public:
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Please separate with empty line.


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Comment at: clang-tidy/altera/KernelNameRestrictionCheck.cpp:46
+};
+} // namespace
+
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Please separate with empty line.


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Comment at: docs/ReleaseNotes.rst:79
+
+    Checks for cases where the kernel source file is named "kernel.cl",
+      "Verilog.cl", or "VHDL.cl".
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Please fix indentation and use single back-ticks to highlight file names. Same in documentation.


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Comment at: docs/clang-tidy/checks/altera-kernel-name-restriction.rst:13
+
+As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA SDK 
+for OpenCL Pro Edition: Programming Guide."
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May be link is better?


Repository:
  rCTE Clang Tools Extra

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72218/new/

https://reviews.llvm.org/D72218