[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:36
+// The only physical register that isn't saved is x2 (SP), which is used by the
+// processor when the interrupt happens.
+
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Nitpick: "the interrupt happens" -> "an interrupt happens" (or, even better, "is serviced").


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Comment at: llvm/test/CodeGen/RISCV/calling-conv-ilp32e-double-bug.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -mattr=+f -verify-machineinstrs < %s
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It would be good to describe in a comment what the bug is.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70401/new/

https://reviews.llvm.org/D70401