[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands
Kerry McLaughlin via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Aug 15 09:02:55 PDT 2019
kmclaughlin created this revision.
kmclaughlin added reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov.
Herald added subscribers: psnobl, rkruppe, tschuett, javed.absar.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
Adds the following inline asm constraints for SVE:
- w: SVE vector register with full range, Z0 to Z31
- x: Restricted to registers Z0 to Z15 inclusive.
- y: Restricted to registers Z0 to Z7 inclusive.
This change also adds the "z" modifier to interpret a register as an SVE register.
Not all of the bitconvert patterns added by this patch are used, but they have been included here for completeness.
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