[PATCH] D65500: [RISCV] Support 'f' Inline Assembly Constraint
Sam Elliott via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed Jul 31 00:10:26 PDT 2019
lenary created this revision.
lenary added reviewers: asb, lewis-revill.
Herald added subscribers: llvm-commits, cfe-commits, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
Herald added projects: clang, LLVM.
This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
This patch adds support in both the clang frontend, and LLVM itself.
rG LLVM Github Monorepo
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