[PATCH] D64739: [SVE][Inline-Asm] Add support to clang for SVE inline assembly

[Kerry McLaughlin via Phabricator via cfe-commits]

kmclaughlin created this revision.
kmclaughlin added reviewers: erichkeane, sdesmalen, cfe-commits.
Herald added subscribers: psnobl, rkruppe, tschuett, javed.absar.
Herald added a reviewer: rengolin.
Herald added a project: clang.

Adds the SVE vector and predicate registers to the list of known registers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D64739

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/test/CodeGen/aarch64-sve-inline-asm.c


Index: clang/test/CodeGen/aarch64-sve-inline-asm.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-inline-asm.c
@@ -0,0 +1,42 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -target-feature +sve -o - %s | FileCheck %s
+
+long test_z0_p0()
+{
+  long t;
+
+  asm volatile(
+    "ptrue p0.d\n"
+    "dup z0.d, #3\n"
+    "smaxv %d0, p0, z0.d\n"
+  : "=w" (t) : : "z0", "p0");
+// CHECK: call i64 asm sideeffect "ptrue p0.d\0Adup z0.d, #3\0Asmaxv ${0:d}, p0, z0.d\0A", "=w,~{z0},~{p0}"
+
+  return t;
+}
+
+long test_z31()
+{
+  long t;
+
+  asm volatile(
+    "ptrue p0.d\n"
+    "dup z31.d, #3\n"
+    "uaddv %d0, p0, z31.d\n"
+  : "=w" (t) : : "z31", "p0");
+// CHECK: call i64 asm sideeffect "ptrue p0.d\0Adup z31.d, #3\0Auaddv ${0:d}, p0, z31.d\0A", "=w,~{z31},~{p0}"
+
+  return t;
+}
+
+long test_p15()
+{
+  long t = 0;
+
+  asm volatile(
+    "ptrue p15.h\n"
+    "incp %x0, p15.h\n"
+  : "=r" (t) : "0" (t) : "p15");
+// CHECK: call i64 asm sideeffect "ptrue p15.h\0Aincp ${0:x}, p15.h\0A", "=r,0,~{p15}"
+
+  return t;
+}
Index: clang/lib/Basic/Targets/AArch64.cpp
===================================================================
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -304,20 +304,29 @@
     "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
     "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
 
-    // 32-bit floating point regsisters
+    // 32-bit floating point registers
     "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
     "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
     "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
 
-    // 64-bit floating point regsisters
+    // 64-bit floating point registers
     "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
     "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
     "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
 
-    // Vector registers
+    // Neon vector registers
     "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
     "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
-    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
+    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
+
+    // SVE vector registers
+    "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
+    "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
+    "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
+
+    // SVE predicate registers
+    "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
+    "p11", "p12", "p13", "p14", "p15"
 };
 
 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {


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