[PATCH] D49754: Add -m(no-)spe, and e500 CPU definitions and support to clang

[Kei Thomsen via Phabricator via cfe-commits]

kthomsen added a comment.

@vit9696 I'm working since 3 days on that issue, and found nothing... PPCISelLowering.cpp has 2 functions: LowerVASTART() and LowerVAARG(). LowerVASTART is correctly called (store the GPR to the internal va_list structure), but LowerVAARG is never called and I don't understand why. The generated code is exactly what the LowerVAARG source is shown, but it must be generated somewhere else.
The Problem is the following:
The calling function is correctly placing the double date into a register pair (r5/r6 or r7/r8). In the function all registers (GPR) are placed on the stack (by LowerVASTART) and it reserves space for the FPU registers to save (which SPE don't have and therefore this space is left empty). The va_arg is now getting the double parameter from that FPU area (it has an offset of 32 to the GPR space), but not from the GPR space.
I am searching for that code generation. I'm 99% sure LowerVAARG can generate that code, but 100% sure that LowerVAARG is not called. Therefore, where is the va_arg loading generated? 
My test code:

  typedef __builtin_va_list va_list;
  double a;
  long l = 0;
  
  void pr(char *txt, ...)
  {
      va_list vp;
  
      __builtin_va_start(vp,txt);
      a = __builtin_va_arg(vp,double);
      l = __builtin_va_arg(vp,long);
      __builtin_va_end(vp);
  }

@vit9696 if you like, you can contact me directly, so that we can coordinate our work on the SPE. thomsen at microsys.de
Kei


Repository:
  rC Clang

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  https://reviews.llvm.org/D49754/new/

https://reviews.llvm.org/D49754