[PATCH] D41523: xmmintrin.h documentation fixes and updates
Katya Romanova via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jan 4 19:29:30 PST 2018
kromanova added inline comments.
Comment at: lib/Headers/xmmintrin.h:2199
-/// This intrinsic corresponds to the <c> VPINSRW / PINSRW </c> instruction.
+/// This intrinsic corresponds to the <c> PINSRW </c> instruction.
> Why is VPINSRW removed?
I suspect the rational is the same I talked about in mmintrin.h review.
This intrinsic should use MMX registers and shouldn't have corresponding AVX instruction(s).
I've tried this and with or without -mavx for Linux/x86_64 we generate PINSRW in both cases (i.e. I wasn't able to trigger generation of VEX prefixed instruction).
__m64 foo (__m64 a, int b)
x = _mm_insert_pi16 (a, b, 0);
Comment at: lib/Headers/xmmintrin.h:2659
-/// This intrinsic corresponds to the <c> VMOVSS / MOVSS </c> instruction.
+/// This intrinsic corresponds to the <c> VBLENDPS / BLENDPS </c> instruction.
> MOVSS is correct for pre SSE4.1 targets.
Doug, I think we should write:
VBLENDPS / BLENDPS / MOVSS
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