[PATCH] Implement aarch64 neon instruction class AdvSIMD (by element) - LLVM

Jiangning Liu liujiangning1 at gmail.com
Sun Sep 29 20:34:52 PDT 2013


Actually I already added a new test 
http://llvm-reviews.chandlerc.com/D1753#dd97ddbf to check fmla will not 
be generated when -fp-contract=fast is not in command line, although I'm 
using CHECK rather than CHECK-NOT.

; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu 
-mattr=+neon | FileCheck %s

define <2 x float> @test_vfma_lane_f32(<2 x float> %a, <2 x float> %b, 
<2 x float> %v) {
; CHECK: test_vfma_lane_f32:
; CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[{{[0-9]+}}]
; CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
   %shuffle = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> 
<i32 1, i32 1>
   %mul = fmul <2 x float> %shuffle, %b
   %add = fadd <2 x float> %mul, %a
   ret <2 x float> %add


On 09/30/2013 01:52 AM, Tim Northover wrote:
> Hi Jiangning,
> Sorry I didn't get a chance to reply on Friday, and thanks for
> reworking the patch.
>>    For register definition 'Re', I didn't make change.
> Fair enough.
> I think it looks pretty much OK now, though I'd be happier if there
> was a test that we *weren't* generating fmla instructions all the time
> (perhaps with a comment about it being intentional). It's a very
> tempting "optimisation" to make.
> I think you should commit, with or without that though. I'll take a
> look over the revision after-wards.
> Cheers.
> Tim.

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