[PATCH][AArch64] implement aarch64 neon load/store instructions class AdvSIMD (lselem)

[Hao Liu]

Ping.

 

If there is some problem, I can improve it.

 

Thanks,

-Hao

From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Hao Liu
Sent: Wednesday, September 18, 2013 2:31 PM
To: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
Subject: [PATCH][AArch64] implement aarch64 neon load/store instructions
class AdvSIMD (lselem)

 

Hi folks,

 

Attached are patches to implement aarch64 neon instruction class AdvSIMD
(lselem), which are all structure load/store instructions: ld1/st1, ld2/st2,
ld3/st3, ld4/st4.

 

(1) The implementation is like ARMv7, and the main change is removing the
code about sub registers. The dag selection phase is implemented directly in
AArch64ISelDAGToDAG not in table.   

 

(2) As the representation for a vector list has two types:

             {v0.8b - v3.8b}

     {v0.8b, v1.8b, v2.8b, v3.8b}

and both types are correct, I add a function in AArch64AsmParser.cpp to make
it can recognize both types. And the second type is chose as output
representation.

 

Actually, I'm not very familiar with load/store instructions and they are
quite different from other instructions. Although the implementation is like
ARMv7 but AArch64 also has much difference from ARMv7, I'm not sure whether
the implementation is  correct.

 

Please review this patch.

 

Thanks,

-Hao
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