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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='color:#1F497D'>Ping…<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>If there is some problem, I can improve it.<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='color:#1F497D'>-Hao<o:p></o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> llvm-commits-bounces@cs.uiuc.edu [mailto:llvm-commits-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Hao Liu<br><b>Sent:</b> Wednesday, September 18, 2013 2:31 PM<br><b>To:</b> llvm-commits@cs.uiuc.edu; cfe-commits@cs.uiuc.edu<br><b>Subject:</b> [PATCH][AArch64] implement aarch64 neon load/store instructions class AdvSIMD (lselem)<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hi folks,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Attached are patches to implement aarch64 neon instruction class AdvSIMD (lselem), which are all structure load/store instructions: ld1/st1, ld2/st2, ld3/st3, ld4/st4.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>(1) The implementation is like ARMv7, and the main change is removing the code about sub registers. The dag selection phase is implemented directly in AArch64ISelDAGToDAG not in table. <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>(2) As the representation for a vector list has two types:<o:p></o:p></p><p class=MsoNormal style='margin-left:.2in'> {v0.8b – v3.8b}<o:p></o:p></p><p class=MsoListParagraph style='margin-left:.45in'> {v0.8b, v1.8b, v2.8b, v3.8b}<o:p></o:p></p><p class=MsoNormal>and both types are correct, I add a function in AArch64AsmParser.cpp to make it can recognize both types. And the second type is chose as output representation.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Actually, I’m not very familiar with load/store instructions and they are quite different from other instructions. Although the implementation is like ARMv7 but AArch64 also has much difference from ARMv7, I’m not sure whether the implementation is correct.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Please review this patch.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Thanks,<o:p></o:p></p><p class=MsoNormal>-Hao<o:p></o:p></p></div></body></html>